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The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up

to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface

supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1),

GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general

purpose interface supports up to 248 I/O pins.

For more details about features and additional description information on the device General-Purpose Interface,

see the corresponding sections within Signal Descriptions and Detailed Description.

Note

The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.

Table 6-38, Section 6.10.5.9.1, and Section 6.10.5.9.2 present timing conditions, requirements, and switching

characteristics for GPIO.

Table 6-38. GPIO Timing Conditions

PARAMETER

BUFFER TYPE

MIN

MAX UNIT

INPUT CONDITIONS

SRI

Input slew rate

LVCMOS

0.2

6.6

V/ns

I2C OD FS

0.2

0.8

V/ns

OUTPUT CONDITIONS

Output load capacitance

LVCMOS

I2C OD FS

100

6.10.5.9.1 GPIO Timing Requirements

NO.

BUFFER TYPE

MIN

MAX UNIT

GPIO1 tw(gpio_in)

Pulse width, GPIOn_x

1.8 V

2P + 2.6(1)

3.3 V

2P + 3.4(1)

(1)

P = functional clock period in ns.

6.10.5.9.2 GPIO Switching Characteristics

NO.

PARAMETER

BUFFER TYPE

MIN

MAX

UNIT

GPIO3 tw(GPIO_OUT)

Minimum Output Pulse Width

LVCMOS

–3.6 + 0.975P(1)

GPIO4 tw(GPIO_OUT)

Minimum Output Pulse Width Low

I2C Open Drain

160

GPIO5 tw(GPIO_OUT)

Minimum Output Pulse Width High

I2C Open Drain

(1)

P = functional clock period in ns.

For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

6.10.5.10 GPMC

For more details about features and additional description information on the device General-Purpose Memory

Controller, see the corresponding sections within Signal Descriptions and Detailed Description.

Table 6-39 represents GPMC timing conditions.

Note

The IO timings provided in this section are applicable for all combinations of signals for GPMC0.

However, the timings are only valid for GPMC0 if signals within a single IOSET are used. The IOSETs

are defined in the GPMC0_IOSET, GPMC0_IOSET table.

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AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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