AM69 datasheet(243/312 Pages) TI

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SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (OUT)

SPI_CS[i] (OUT)

SPI_SCLK (OUT)

SPI_D[x] (OUT)

Bit n-1

Bit n-2

Bit n-3

Bit n-4

Bit 0

Bit n-1

Bit n-2

Bit n-3

Bit 1

Bit0

PHA=0

EPOL=1

POL=0

POL=1

PHA=1

EPOL=1

POL=0

POL=1

SM8

SM9

SM6

SM3

SM1

SM2

SM1

SM8

SM9

SM3

SM1

SM2

SM1

SM6

SM7

SM6

SM2

SM3

SM2

SM3

SM6

SPRSP08_TIMING_McSPI_01

Figure 6-74. MCSPI Controller Mode Transmit Timing

6.10.5.16.2 MCSPI — Peripheral Mode

Table 6-53, Table 6-54, Figure 6-75, and Figure 6-76 present timing requirements and switching characteristics

for MCSPI – Peripheral Mode.

Table 6-53. MCSPI Timing Requirements - Peripheral Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

SS1

tc(spiclk)

Cycle time, SPI_CLK

20.8

SS2

tw(spiclkL)

Pulse duration, SPI_CLK low

0.45P(1)

SS3

tw(spiclkH)

Pulse duration, SPI_CLK high

0.45P(1)

SS4

tsu(simoV-spiclkV)

Setup time, SPI_D[x] valid before SPI_CLK active edge

SS5

th(spiclkV-simoV)

Hold time, SPI_D[x] valid after SPI_CLK active edge

SS8

tsu(csV-spiclkV)

Setup time, SPI_CSi valid before SPI_CLK first edge

SS9

th(spiclkV-csV)

Hold time, SPI_CSi valid after SPI_CLK last edge

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AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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