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6.10.5.19.1.2.2 OSPI Switching Characteristics – SDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

7.5

tw(CLKL)

Pulse duration, CLK low

–0.3+0.475*P

(2)

Pulse duration, CLK high

–0.3+0.475*P

(2)

O10 ttd(CSn-CLK)

Delay time, CSn[3:0] active edge to CLK rising

edge

1.8V

0.475 * P +

0.975 * M * R

- 7 (2) (3) (5)

0.525 * P +

1.025 * M * R

+ 1 (2) (3) (5)

3.3V

0.475 * P +

0.975 * M * R

- 7(2) (3) (5)

0.525 * P +

1.025 * M * R

+ 1 (2) (3) (5)

O11 td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

0.475 * P +

0.975 * N * R

- 1 (2) (4) (5)

0.525 * P +

1.025 * N * R

+ 1 (2) (4) (5)

3.3V

0.475 * P +

0.975 * N * R

- 1 (2) (4) (5)

0.525 * P +

1.025 * N * R

+ 1(2) (4) (5)

O12 td(CLK-D)

Delay time, CLK active edge to D[i:0]

transition(1)

1.8V

–1.16

1.25

3.3V

–1.33

1.51

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

P = CLK cycle time = SCLK period

(3)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5)

R = refclk

OSPI_CLK

OSPI_TIMING_02

OSPI_CSn

O10

O11

O12

OSPI_D[i:0]

Figure 6-99. OSPI Switching Characteristics – SDR

Section 6.10.5.19.1.2.3, Section 6.10.5.19.1.2.1, Section 6.10.5.19.1.2.2, Section 6.10.5.19.1.2.2, and Figure

6-98 presents timing requirements for OSPI DDR and SDR Mode.

6.10.5.19.1.2.3 OSPI Timing Requirements – DDR Mode

Table 6-84. OSPI DLL Delay Mapping - DDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG

BIT FIELD

OSPI0

OSPI1

DELAY VALUE

TRANSMIT

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x54

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x55

0x5C

RECEIVE

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AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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