AM69 datasheet(264/312 Pages) TI

264 / 312 page

Table 6-84. OSPI DLL Delay Mapping - DDR Timing Modes (continued)

MODE

OSPI_PHY_CONFIGURATION_REG

BIT FIELD

OSPI0

OSPI1

DELAY VALUE

1.8V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x23

0x29

3.3V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x47

0x42

All other modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

Table 6-85. OSPI Timing Requirements – DDR Mode

NO. PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

O15 tsu(D-LBCLK)

Setup time, D[i:0] valid before active LBCLK (DQS)

edge(1)

1.8V, External Board Loopback

0.52

3.3V, External Board Loopback

1.97

O16 th(LBCLK-D)

Hold time, D[i:0] valid after active LBCLK (DQS)

edge(1)

1.8V, External Board Loopback

1.24 (2)

3.3V, External Board Loopback

1.44 (2)

O17 tsu(D-DQS)

Setup time, DQS edge to D[i:0] transition(1)

1.8V, DQS

–0.46

3.3V, DQS

–0.66

O18 th(DQS-D)

Hold time, DQS edge to D[i:0] transition(1)

1.8V, DQS

3.59

3.3V, DQS

8.89

(1)

i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2)

This Hold time requirement is larger than the Hold time provided by a typical flash device. Therefore, the trace length between the

SoC and flash device must be sufficiently long enough to ensure that the Hold time is met at the SoC. Refer to OSPI and QSPI Board

Design and Layout Guidelines for more details.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

Figure 6-100. OSPI Timing Requirements – DDR, External Loopback Clock and DQS

6.10.5.19.1.2.4 OSPI Switching Characteristics – DDR Mode

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, CLK

1.8V

3.3V

tw(CLKL)

Pulse duration, CLK low

0.475*P - 0.3

(2)

tw(CLKH)

Pulse duration, CLK high

0.475*P - 0.3

(2)

td(CLK-CSn)

Delay time, CSn active edge to CLK rising edge

1.8V

0.475 * P +

0.975 * M * R

- 7 (2) (3) (5)

0.525 * P +

1.025 * M * R

+ 1(2) (3) (5)

3.3V

0.475 * P +

0.975 * M * R

- 7(2) (3) (5)

0.525 * P +

1.025 * M * R

+ 1(2) (3) (5)

td(CLK-CSn)

Delay time, CLK rising edge to CSn inactive

edge

1.8V

0.475 * P +

0.975 * N * R

- 7(2) (4) (5)

0.525 * P +

1.025 * N * R

+ 1 (2) (4) (5)

3.3V, OSPI0 DDR TX;

3.3V, OSPI1 DDR TX

0.475 * P +

0.975 * N * R

- 7(2) (4) (5)

0.525 * P +

1.025 * N * R

+ 1 (2) (4) (5)

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

264

Submit Document Feedback

Product Folder Links: AM69A AM69

AM69 Datasheet(PDF) 264 Page - Texas Instruments

AM69 Datasheet(HTML) 264 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL