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10 Peripheral- and Interface-Specific Design Information

10.1 LPDDR4 Board Design and Layout Guidelines

The goal of the Jacinto 7 DDR Board Design and Layout Guidelines is to make the LPDDR4 system

implementation straightforward for all designers. Requirements have been distilled down to a set of layout and

routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.

TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.

10.2 OSPI and QSPI Board Design and Layout Guidelines

The following section details the routing guidelines that must be observed when routing the OSPI and QSPI

interfaces.

10.2.1 No Loopback and Internal Pad Loopback

• The MCU_OSPI[x]_CLK output signal must be connected to the CLK pin of the flash device

• The signal propagation delay from the MCU_OSPI[x]_CLK signal to the flash device must be < 450 ps (~7cm

as stripline or ~8cm as microstrip)

• 50 Ω PCB routing is recommended along with series terminations, as shown in Figure 10-1

• Propagation delays and matching:

– A to B < 450 ps

– Matching skew: < 60 ps

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AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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AM69 Datasheet(PDF) 291 Page - Texas Instruments