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Each odd numbered timer instance from each of the domains may be optionally cascaded with the previous

even numbered timer instance from the same domain to form up to a 64-bit timer. For example, TIMER1 may be

cascaded to TIMER0, MCU_TIMER1 may be cascaded to MCU_TIMER0, etc.

When cascaded, TIMERi acts as a 32-bit prescaler to TIMERi+1, as well as MCU_TIMERn acts as a 32-bit

prescaler to MCU_TIMERn+1. TIMERi / MCU_TIMERn must be configured to generate a PWM output edge at

the desired rate to increment the TIMERi+1/ MCU_TIMERn+1 counter.

For more information, see Timers section in Peripherals chapter in the device TRM.

7.5.5.29 UART

The UART is a slave peripheral that utilizes the DMA for data transfer or interrupt polling via host CPU. There

are twelve UART modules in the device. All UART modules support IrDA and CIR modes when 48 MHz function

clock is used. Each UART can be used for configuration and data exchange with a number of external peripheral

devices or interprocessor communication between devices.

For more information, see Universal Synchronous/Asynchronous Receiver/Transmitter (UART) section in

Peripherals chapter in the device TRM.

7.5.5.30 USB

Similar to earlier versions of USB bus, USB 3.0 is a general-purpose cable bus, supporting data exchange

between a host device and a wide range of simultaneously accessible peripherals.

The device supports two identical USB subsystems:

• USB3SS0 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY

and HS/FS/LS (1) (USB2.0) PHY

• USB3SS1 is SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with on-chip SS (USB3.0) PHY

and HS/FS/LS (USB2.0) PHY

For more information, see Universal Serial Bus (USB) Subsystem section in Peripherals chapter in the device

TRM.

7.5.5.31 UFS

The Universal Flash Storage (UFS) interface is a standard-based serial interface engine.

There is one UFS module inside the device - UFS0. The UFS module includes one UFS 2.1 host controller (HC)

with an integrated M-PHY.

The UFS module complies with the standards as listed in Table 7-1.

Table 7-1. UFS Standards

DOCUMENT

VERSION

DESCRIPTION

JESD220-1A

v1.1

Universal Flash Storage (UFS) Unified Memory Extension

JESD220-2

v1.0

Universal Flash Storage (UFS) Card Extension

JESD220C

v2.1, March 2016

Universal Flash Storage (UFS)

JESD223-1B

v1.1A

Universal Flash Storage Host Controller Interface (UFSHCI) Unified Memory

Extension

JESD223C

v2.1, March 2016

Universal Flash Storage Host Controller Interface (UFSHCI)

JESD224

March 2013

Universal Flash Storage (UFS) Test

November, 2001

Federal Information Processing Standards (FIPS) 197 Advanced Encryption Standard

(AES)

v3.1, 2014

MIPI® Alliance Specification for M-PHY

v1.60, 2013

MIPI Alliance Specification for Unified Protocol (UniProSM)

Revision 24, August 2010

Small Computer System Interface (SCSI) Block Commands - 3

Revision 27, October 2010

SCSI Primary Commands - 4

www.ti.com

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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