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7.5.5.24 OSPI

The Octal Serial Peripheral Interface (OSPI) module is a kind of Serial Peripheral Interface (SPI) module which

allows single, dual, quad or octal read and write access to external flash devices. This module has a memory

mapped register interface, which provides a direct memory interface for accessing data from external flash

devices, simplifying software requirements.

The OSPI module is used to transfer data, either in a memory mapped direct mode (for example a processor

wishing to execute code directly from external flash memory), or in an indirect mode where the module is

set-up to silently perform some requested operation, signalling its completion via interrupts or status registers.

For indirect operations, data is transferred between system memory and external flash memory via an internal

SRAM which is loaded for writes and unloaded for reads by a device master at low latency system speeds.

Interrupts or status registers are used to identify the specific times at which this SRAM should be accessed using

user programmable configuration registers.

For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device

TRM.

7.5.5.25 PCIE

The Peripheral Component Interconnect Express (PCIe) subsystem is built around a multi-lane dual-mode PCIe

controller that provides low pin-count, high reliability, and high-speed data transfers at rates of up to 8.0 Gbps

per lane for serial links on backplanes and printed wiring boards.

For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals

chapter in the device TRM.

7.5.5.26 SerDes

SerDes'es goal is to convert device (SoC) parallel data into serialized data that can be output over a highspeed

electrical interface. In the opposite direction, SerDes converts high-speed serial data into parallel data that can

be processed by the device. To this end, the SerDes contains a variety of functional blocks to handle both the

external analog interface as well as the internal digital logic.

For more information, see Serializer/Deserializer (SerDes) section in Peripherals chapter in the device TRM.

7.5.5.27 WWDT

The Windowed Watchdog Timer provides timer functionality for operating systems and for benchmarking code.

The module incorporates several counters, which define the timebases needed for scheduling in the operating

system. The module is implemented with an RTI module, but only WWDT is supported.

This module is specifically designed to fulfill the requirements for OSEK (“Offene Systeme und deren

Schnittstellen für die Elektronik im Kraftfahrzeug”; “Open Systems and the Corresponding Interfaces for

Automotive Electronics”) as well as OSEK/Time compliant operating systems.

For more information, see Real Time Interrupt (RTI) Module section in Peripherals chapter in the device TRM.

7.5.5.28 Timers

All timers include specific functions to generate accurate tick interrupts to the operating system.

Each timer can be clocked from several different independent clocks. The selection of clock source is made from

registers in the MCU_CTRL_MMR0/CTRL_MMR0.

In the MCU domain the device provides 10 timer pins to be used as MCU Timer Capture inputs or as MCU Timer

PWM outputs. In order to provide maximum flexibility, these 10 pins may be used with any of MCU_TIMER0

through MCU_TIMER9 instances. System level muxes are used to control the capture source pin for each

MCU_TIMER[9-0] and the MCU_TIMER[9-0] source for each MCU_TIMER_IO[1-0] PWM output.

In the MAIN domain the device provides 8 timer pins to be used as Timer Capture inputs or as Timer PWM

outputs. For maximum flexibility, these 8 pins may be used with any of TIMER0 through TIMER19 instances.

System level muxes are used to control the capture source pin for each TIMER[19-0] and the TIMER[19-0]

source for each TIMER_IO[7-0] PWM output.

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

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