TDA4VM21 datasheet(194/331 Pages) TI

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– MCU_CPTS_RFT_CLK — CPTS reference clock inputs for MCU_CPTS_RFT_CLK.

– CPTS_RFT_CLK — CPTS reference clock inputs for CPTS_RFT_CLK.

• External audio reference clock input/output pins

– AUDIO_EXT_REFCLK0

– AUDIO_EXT_REFCLK1

– AUDIO_EXT_REFCLK2

– AUDIO_EXT_REFCLK3

Figure 6-22 shows the external input clock sources and the output clocks to peripherals.

DEVICE

MCU_SYSCLKOUT0

Selects Main PLL output divide-by-6

External main crystal interface pins connected to internal oscillator

which provides reference clock to PLLs within MCU domain

and MAIN domain.

Optional pins to provide reference clock input to the PLLs.

OSC1_XI

OSC1_XO

SYSCLKOUT0

J7ES_CLOCK_01

External Low frequency crystal interface pins connected to internal oscillator

which provides a 32.768 KHz clock for low power operation

in deeper sleep modes.

WKUP_LFOSC0_XI

WKUP_LFOSC0_XO

External Wake-up crystal interface pins connected to internal oscillator

which provides reference clock to PLLs within MAIN domain, and

audio clock frequencies to MCASPs.

WKUP_OSC0_XI

WKUP_OSC0_XO

TCK

MCU_EXT_REFCLK0 / EXT_REFCLK1

Optional external System clock inputs - (MCU domain) / (MAIN domain)

JTAG Clock Input

MCU_CLKOUT0

CLKOUT

Optional for the DPI0/1 Ports of DSS

VOUT[1:0]_EXTPCLKIN

CPTS reference clock input for CPTS_RFT_CLK / MCU_CPTS_RFT_CLK

MCU_CPTS0_RFT_CLK / CPTS0_RFT_CLK

MCU_PORz / PORz

PCIE_REFCLK[3:0]N/P

MCU_RESETz/ RESET_REQz

MCU Warm Reset Input / Device Warm Reset Input

BOOTMODE[7:0]

MCU Power ON Reset / Device Power ON Reset

Boot Mode Configuration / devices select

MCU_BOOTMODE[09:00]

MCU Boot Mode system clock speed and fail-safe boot device

DDR0_CKP/DDR0_CKN

DDR Differential Clock outputs

There are 4 differential clock input/output pins to support PCIe devices

SERDES4_REFCLK_P/N

SerDes reference clock input for PCIe or Optional USB3 and SGMII interfaces

MCU_OBSCLK0 / OBSCLK[2:0]

Observation clock outputs for MCU Domain clock / MAIN Domain clocks

External audio reference clock input/output pins

AUDIO_EXT_REFCLK[3:0]

Reference clock output for Ethernet PHYs (50MHz or 25MHz)

Reference clock output

Figure 6-22. Input Clocks Interface

TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

www.ti.com

194

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TDA4VM21 Datasheet(PDF) 194 Page - Texas Instruments

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