TDA4VM21 datasheet(197/331 Pages) TI

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J7ES_WKUP_OSC_CC_05

PCBXI

PCBXO

PCB

Signal Traces

Crystal Circuit

Components

WKUP_OSC0_XO

WKUP_OSC0_XI

Device

Figure 6-25. Load Capacitance

Load capacitors, CL1 and CL2 in Figure 6-23, should be chosen such that the below equation is satisfied. CL in

the equation is the load specified by the crystal manufacturer.

CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]

To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the

combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to

determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO =

0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) -

(CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF

6.9.4.1.1.2 Shunt Capacitance

The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for

WKUP_OSC0 operating conditions defined in Table 6-29. Shunt capacitance, Cshunt, of the crystal circuit is a

combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal

circuit components to WKUP_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the

PCB designer should be able to extract mutual parasitic capacitance between these signal traces. The device

package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined

in Table 6-30.

PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is

typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can

also be minimized by placing a ground trace between these signals when the layout requires them to be routed

in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as

possible when selecting a crystal.

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TDA4VM-Q1, TDA4VM

SPRSP36K – SEPTEMBER 2021 – REVISED APRIL 2024

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TDA4VM21 Datasheet(PDF) 197 Page - Texas Instruments