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TDP142 Datasheet(PDF) 15 Page - Texas Instruments |
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TDP142 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 39 page ![]() 6.4.4 Operation Timing – Power Up CFG pins VCC Internal Power Good TDP142 td_pg tcfg_su tcfg_hd Figure 6-1. Power-Up Timing Table 6-3. Power-Up Timing (1) (2) PARAMETER MIN MAX UNIT td_pg VCC (minimum) to Internal Power Good asserted high 500 µs tcfg_su CFG(1) pins setup(2) 50 µs tcfg_hd CFG(1) pins hold 10 µs tVCC_RAMP VCC supply ramp requirement 100 ms (1) Following pins comprise CFG pins: I2C_EN, DPEQ[1:0]. (2) Recommend CFG pins are stable when VCC is at min. www.ti.com TDP142-Q1 SLLSG10 – NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: TDP142-Q1 |
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