7 Register Maps

7.1 TDP142-Q1 Registers

Table 7-1 lists the TDP142-Q1 registers. All register offset addresses not listed in Table 7-1 should be

considered as reserved locations and the register contents should not be modified.

Table 7-1. TDP142-Q1 Registers

Offset

Acronym

Register Name

Section

0xA

General_1

General Register

Go

0x10

DP01EQ_SEL

DisplayPort Lane 0 and 1 EQ Control

Go

0x11

DP23EQ_SEL

DisplayPort Lane 2 and 3 EQ Control

Go

0x12

DisplayPort_1

AUX Snoop Status

Go

0x13

DisplayPort_2

DP Lane Enable/Disable Control

Go

0x32

VOD_CTRL

VOD Linearity

Go

Complex bit access types are encoded to fit into small table cells. Table 7-2 shows the codes that are used for

access types in this section.

Table 7-2. TDP142-Q1 Access Type Codes

Access Type

Code

Description

Read Type

R

R

Read

RH

R

H

Read

Set or cleared by hardware

Write Type

W

W

Write

W1S

W

1S

Write

1 to set

WS

W

Write

Reset or Default Value

-n

Value after reset or the default

value

7.1.1 General_1 Register (Offset = 0xA) [reset = 0x1]

General_1 is shown in Table 7-3.

Return to the Summary Table.

This register is used to select between disabled and DisplayPort modes. Software can set the EQ_OVERRIDE

bit to use the EQ registers instead of pins.

Table 7-3. General_1 Register Field Descriptions

Bit

Field

Type

Reset

Description

7

RESERVED

R/W

0x0

Reserved

6

RESERVED

R

0x0

Reserved

5

SWAP_HPDIN

R/W

0x0

Controls which pin HPDIN is derived from.

0x0 = HPDIN is in default location

0x1 = HPDIN location is swapped (PIN 23 to PIN 32, or PIN 32 to

PIN 23).

TDP142-Q1

SLLSG10 – NOVEMBER 2024

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