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TDP142 Datasheet(PDF) 3 Page - Texas Instruments |
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TDP142 Datasheet(HTML) 3 Page - Texas Instruments |
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3 / 39 page ![]() 4 Pin Configuration and Functions Thermal pad 1 INDP1p 2 INDP1n 3 A0 4 INDP0p 5 INDP0n 6 DPEQ0/A1 7 INDP2p 8 INDP2n 9 I2C_EN 10 INDP3p 11 INDP3n 12 VCC 21 SNOOPENZ/RSVD8 22 OUTDP3p 23 OUTDP3n 24 HPDIN/RSVD9 25 OUTDP2p 26 OUTDP2n 27 RSVD10 28 OUTDP0n 29 OUTDP0p 30 RSVD11 31 OUTDP1n 32 OUTDP1p Not to scale Figure 4-1. RGF Package 40-Pin (VQFN) Top View Table 4-1. Pin Functions PIN I/O DESCRIPTION NAME NO. INDP0p 1 I DP Differential positive input for DisplayPort Lane 0. INDP0n 2 I DP Differential negative input for DisplayPort Lane 0. A0 3 4 Level I When I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin also sets the TDP142-Q1 I2C address. See Table 6-4. If I2C_EN = “F”, then this pin must be set to “F” or “0”. INDP1p 4 Diff I DP Differential positive input for DisplayPort Lane 1. INDP1n 5 Diff I DP Differential negative input for DisplayPort Lane 1. DPEQ0/A1 6 4 Level I DisplayPort Receiver EQ control. This along with DPEQ1 selects the DisplayPort receiver equalization gain. Refer to Table 6-2 for equalization settings. When I2C_EN is not ‘0’, this pin also sets the TDP142-Q1 I2C address. See Table 6-4. INDP2p 7 Diff I DP Differential positive input for DisplayPort Lane 2. INDP2n 8 Diff I DP Differential negative input for DisplayPort Lane 2. www.ti.com TDP142-Q1 SLLSG10 – NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: TDP142-Q1 |
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