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TDP142 Datasheet(PDF) 19 Page - Texas Instruments

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Part # TDP142
Description  TDP142-Q1 DisplayPort™ 8.1Gbps Linear Redriver
PDF  39 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TDP142 Datasheet(HTML) 19 Page - Texas Instruments

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Table 7-3. General_1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
EQ_OVERRIDE
R/W
0x0
Setting this field allows software to use EQ settings from registers
instead of value sampled from pins.
0x0 = EQ settings based on sampled state of EQ pins.
0x1 = EQ settings based on programmed value of each of the EQ
registers.
3
HPDIN_OVERRIDE
R/W
0x0
Overrides HPDIN pin state.
0x0 = HPD_IN based on HPD_IN pin.
0x1 = HPD_IN high.
2
RESERVED
R/W
0x0
RESERVED
1-0
CTLSEL
R/W
0x1
Upon power-on, software must write 0x2 to enable DisplayPort
functionality. If DisplayPort funcitonality is not required, then software
must write 0x0 to disable DisplayPort
0x0 = Disabled. DP disabled and lowest power state
0x1 = DP disabled but not lowest power state.
0x2 = DisplayPort enabled.
0x3 = Reserved
7.1.2 DP01EQ_SEL Register (Offset = 0x10) [reset = 0x0]
DP01EQ_SEL is shown in Table 7-4.
Return to the Summary Table.
This register controls the receiver equalization setting for the DisplayPort receivers 0 and 1.
Table 7-4. DP01EQ_SEL Register Field Descriptions
Bit
Field
Type
Reset
Description
7-4
DP1EQ_SEL
RH/W
0x0
Field selects EQ for DP lane 1 pins. When EQ_OVERRIDE =
0b, this field reflects the sampled state of DPEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for DP
Lane 1 based on value written to this field.
3-0
DP0EQ_SEL
RH/W
0x0
Field selects EQ for DP lane 0 pins. When EQ_OVERRIDE =
0b, this field reflects the sampled state of DPEQ[1:0] pins. When
EQ_OVERRIDE = 1b, software can change the EQ setting for DP
Lane 0 based on value written to this field.
7.1.3 DP23EQ_SEL Register (Offset = 0x11) [reset = 0x0]
DP23EQ_SEL is shown in Table 7-5.
Return to the Summary Table.
This register controls the receiver equalization setting for the DisplayPort receivers 2 and 3.
www.ti.com
TDP142-Q1
SLLSG10 – NOVEMBER 2024
Copyright © 2024 Texas Instruments Incorporated
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