6.5 Programming

For further programmability, the TDP142-Q1 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA

pins are used for I2C clock and I2C data, respectively.

Table 6-4. TDP142-Q1 I2C Target Address

DPEQ0/A1

PIN LEVEL

A0

PIN LEVEL

BIT 7 (MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0 (W/R)

0

0

1

0

0

0

1

0

0

0/1

0

R

1

0

0

0

1

0

1

0/1

0

F

1

0

0

0

1

1

0

0/1

0

1

1

0

0

0

1

1

1

0/1

R

0

0

1

0

0

0

0

0

0/1

R

R

0

1

0

0

0

0

1

0/1

R

F

0

1

0

0

0

1

0

0/1

R

1

0

1

0

0

0

1

1

0/1

F

0

0

0

1

0

0

0

0

0/1

F

R

0

0

1

0

0

0

1

0/1

F

F

0

0

1

0

0

1

0

0/1

F

1

0

0

1

0

0

1

1

0/1

1

0

0

0

0

1

1

0

0

0/1

1

R

0

0

0

1

1

0

1

0/1

1

F

0

0

0

1

1

1

0

0/1

1

1

0

0

0

1

1

1

1

0/1

Use the following procedure to write to TDP142-Q1 I2C registers:

1. The controller initiates a write operation by generating a start condition (S), followed by the TDP142-Q1 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TDP142-Q1 acknowledges the address cycle.

3. The controller presents the sub-address (I2C register within TDP142-Q1) to be written, consisting of one byte

of data, MSB-first.

4. The TDP142-Q1 acknowledges the sub-address cycle.

5. The controller presents the first byte of data to be written to the I2C register.

6. The TDP142-Q1 acknowledges the byte transfer.

7. The controller can continue presenting additional bytes of data to be written, with each byte transfer

completing with an acknowledge from the TDP142-Q1.

8. The controller terminates the write operation by generating a stop condition (P).

Use the following procedure to read the TDP142-Q1 I2C registers:

1. The controller initiates a read operation by generating a start condition (S), followed by the TDP142-Q1 7-bit

address and a one-value “W/R” bit to indicate a read cycle.

2. The TDP142-Q1 acknowledges the address cycle.

3. The TDP142-Q1 transmit the contents of the memory registers MSB-first starting at register 00h or last read

sub-address+1. If a write to the T I2C register occurred prior to the read, then the TDP142-Q1 starts at the

sub-address specified in the write.

4. The TDP142-Q1 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the controller

after each byte transfer; the I2C controller acknowledges reception of each data byte transfer.

5. If an ACK is received, the TDP142-Q1 transmits the next byte of data.

6. The controller terminates the read operation by generating a stop condition (P).

TDP142-Q1

SLLSG10 – NOVEMBER 2024

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