 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TDP142 Datasheet(PDF) 20 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TDP142 Datasheet(HTML) 20 Page - Texas Instruments |
|
|
20 / 39 page  Table 7-5. DP23EQ_SEL Register Field Descriptions Bit Field Type Reset Description 7-4 DP3EQ_SEL RH/W 0x0 Field selects EQ for DP lane 3 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 3 based on value written to this field. 3-0 DP2EQ_SEL RH/W 0x0 Field selects EQ for DP lane 2 pins. When EQ_OVERRIDE = 0b, this field reflects the sampled state of DPEQ[1:0] pins. When EQ_OVERRIDE = 1b, software can change the EQ setting for DP Lane 2 based on value written to this field. 7.1.4 DisplayPort_1 Register (Offset = 0x12) [reset = 0x0] DisplayPort_1 is shown in Table 7-6. Return to the Summary Table. This register provides status of AUX snooping when AUX Snooping is enabled. Table 7-6. DisplayPort_1 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R 0x0 Reserved 6-5 SET_POWER_STATE RH 0x0 This field represents the snooped value of the AUX write to DPCD address 0x00600. When AUX_SNOOP_DISABLE = 0b, the enable/disable of DP lanes based on the snooped value. When AUX_SNOOP_DISABLE = 1b, then DP lane enable/disable are determined by state of DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b. 4-0 LANE_COUNT_SET RH 0x0 This field represents the snooped value of AUX write to DPCD address 0x00101 register. When AUX_SNOOP_DISABLE = 0b, DP lanes enabled specified by the snoop value. Unused DP lanes is disabled to save power. When AUX_SNOOP_DISABLE = 1b, then DP lanes enable/disable are determined by DPx_DISABLE registers, where x = 0, 1, 2, or 3. This field is reset to 0h by hardware when CTLSEL1 changes from a 1b to a 0b. 7.1.5 DisplayPort_2 Register (Offset = 0x13) [reset = 0x0] DisplayPort_2 is shown in Table 7-7. Return to the Summary Table. This register provides controls for enabling and disabling AUX snooping and individual DP lanes. Table 7-7. DisplayPort_2 Register Field Descriptions Bit Field Type Reset Description 7 AUX_SNOOP_DISABLE R/W 0x0 Controls whether DP lanes are enabled based on AUX snooped value or registers. 0x0 = AUX snoop enabled. 0x1 = AUX snoop disabled. DP lanes are controlled by registers. 6 RESERVED R 0x0 Reserved TDP142-Q1 SLLSG10 – NOVEMBER 2024 www.ti.com 20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TDP142-Q1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
