AM67 datasheet(133/237 Pages) TI

133 / 237 page

6.9.5.6 DDRSS

For more details about features and additional description information on the device LPDDR4 Memory Interface,

see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Table 6-43 and Figure 6-35 present switching characteristics for DDRSS.

Table 6-43. DDRSS Switching Characteristics

see Figure 1-1

NO.

PARAMETER

DDR TYPE

CORE VOLTAGE

MIN

MAX UNIT

tc(DDR_CKP/

DDR_CKN)

Cycle time, DDR_CKP and DDR_CKN

LPDDR

0.75-V Operation

0.536(1)

0.85-V Operation

.500(1)

(1)

Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.

TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,

PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 LPDDR4 Board Design and Layout

Guidelines for details.

DDR0_CKP

DDR0_CKN

Figure 6-35. DDRSS Switching Characteristics

For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

www.ti.com

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

Submit Document Feedback

133

Product Folder Links: AM67 AM67A

AM67 Datasheet(PDF) 133 Page - Texas Instruments