AM67 datasheet(134/237 Pages) TI

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6.9.5.7 DSS

Table 6-44, Table 6-45, Figure 6-36, Table 6-46 and Figure 6-37 present timing conditions, timing requirements,

and switching characteristics for DSS.

Table 6-44. DSS Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

1.44

26.4

V/ns

OUTPUT CONDITIONS

Output load capacitance

1.5

PCB CONNECTIVITY REQUIREMENTS

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

Table 6-45. DSS External Pixel Clock Timing Requirements

see Figure 6-36

NO.

MIN

MAX

UNIT

tc(extpclkin)

Cycle time, VOUT(x)_EXTPCLKIN(2)

6.06

tw(extpclkinL)

Pulse duration, VOUT(x)_EXTPCLKIN(2) low

0.475P(1)

tw(extpclkinH)

Pulse duration, VOUT(x)_EXTPCLKIN(2) high

0.475P(1)

(1)

P = VOUT(x)_EXTPCLKIN cycle time in ns

(2)

x in VOUT(x) = 0

VOUT(x)_EXTPCLKIN

DPI_TIMING_02

Falling-edge Clock Reference

Rising-edge Clock Reference

VOUT(x)_EXTPCLKIN

Figure 6-36. DSS External Pixel Clock Timing Requirements

AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

www.ti.com

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