AM67 datasheet(135/237 Pages) TI

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Table 6-46. DSS Switching Characteristics

see Figure 6-37

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(pclk)

Cycle time, VOUT(x)_PCLK(2)

6.06

tw(pclkL)

Pulse duration, VOUT(x)_PCLK(2) low

Internal PLL 0.475P(1) - 0.3

EXTPCLKIN

Y(3) - 0.45

tw(pclkH)

Pulse duration, VOUT(x)_PCLK(2) high

Internal PLL

0.475P(1) -0.3

EXTPCLKIN

Z(4) - 0.45

td(pclkV-dataV)

Delay time, VOUT(x)_PCLK(2) transition to

VOUT(x)_DATA[23:0](2) transition

Internal PLL

-0.68

1.78

EXTPCLKIN

-0.68

1.78

td(pclkV-ctrlL)

Delay time, VOUT(x)_PCLK(2) transition to control signals

VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2)

falling edge

Internal PLL

-0.68

1.78

EXTPCLKIN

-0.68

1.78

(1)

P = VOUT(x)_PCLK cycle time in ns

(2)

x in VOUT(x) = 0

(3)

Y = tw(extpclkinL), parameter D7 from Table 6-45, DSS External Pixel Clock Timing Requirements

(4)

Z = tw(extpclkinH), parameter D8 from Table 6-45, DSS External Pixel Clock Timing Requirements

VOUT(x)_PCLK

VOUT(x)_VSYNC

VOUT(x)_HSYNC

VOUT(x)_DATA[23:0]

VOUT(x)_DE

data_1 data_2

data_n

DPI_TIMING_01

VOUT

_PCLK

(x)

Falling-edge Clock Reference

Rising-edge Clock Reference

The assertion of data can be programmed to occur on the falling or rising edge of the pixel clock. Refer to Display Subsystem (DSS)

section in Peripherals chapter in the device TRM.

The polarity and pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section

in Peripherals chapter in the device TRM.

The VOUT(x)_PCLK frequency is configurable, refer to Display Subsystem section in Peripherals chapter in the device TRM.

Figure 6-37. DSS Switching Characteristics

For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the

device TRM.

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AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

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