AKD4635 datasheet(28/81 Pages) AKM

28 / 81 page

[AK4635]

Rev. 0.6

2007/10

- 28 -

■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)

When an external clock (12MHz, 13.5MHz, 24MHz or 27MHz) is input to the MCKI pin, the MCKO, BICK and FCK

clocks are generated by an internal PLL circuit. The MCKO output frequency is fixed to 256fs, the output is enabled by

MCKO bit. The BICK is selected among 16fs, 32fs or 64fs, by BCKO1-0 bits. (Table 9)

In DSP mode, FCK output can select Duty 50% or High-output only during 1 BICK cycle (Table 10). Except DSP mode,

FCKO bit should be set “0”.

When BICK output frequency is 16fs, the audio interface format supports Mode 0 only (DSP Mode).

AK4635

DSP or

μP

MCKO

BICK

FCK

SDTO

SDTI

BCLK

FCK

SDTI

SDTO

MCKI

1fs

16fs, 32fs, 64fs

256fs

12MHz, 13.5MHz,

24MHz, 27MHz

MCLK

Figure 23. PLL Master Mode

Mode

BCKO1

BCKO0

BICK Output

Frequency

16fs

(default)

32fs

64fs

N/A

Table 9. BICK Output Frequency at Master Mode

Mode

FCKO

FCK Output

Duty = 50%

(default)

High Width = 1/fBCK

fBCK is BICK Output Frequency.

Table 10. FCK Output at PLL Master Mode and DSP Mode

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