AKD4635 datasheet(77/81 Pages) AKM

77 / 81 page

[AK4635]

Rev. 0.6

2007/10

- 77 -

SYSTEM DESIGN

Figure 63 and Figure 64 show the system connection diagram. The evaluation board [AKD4635] demonstrates the

optimum layout, power supply arrangements and measurement results.

< MIC Single-end Input >

Top View

AVDD

MCKO

Analog Supply

2.8

∼3.6V

0.1µ

2.2k

Speaker

0.1µ

DSP

µP

ZD1

VSS1

VSAG

VIN

PDN

CSN

VOUT

VCOM

VCOC

FCKCCLKCDTI

MPI

MIC

LIN

AOUT

MCKI

SDTI

BICK

VSS3

VSS2

DVDD

I2C

SPP

SVDD

SPN

SDTO

0.1µ

10µ

0.1µ

2.2µ

1µ

220

20 k

ZD2

0.1µ

Dynamic SPK

R1, R2: Short

ZD1, ZD2: Open

Piezo SPK

R1, R2:

≥10Ω

ZD1, ZD2: Required

1µ

Figure 63. Typical Connection Diagram

Notes:

- VSS1, VSS2 and VSS3 of the AK4635 should be distributed separately from the ground of external controllers.

- All digital input pins except pull-down pin should not be left floating.

- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.

- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 48.

- When the AK4635 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.

Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4635.

-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.

AKD4635 Datasheet(PDF) 77 Page - Asahi Kasei Microsystems

AKD4635 Datasheet(HTML) 77 Page - Asahi Kasei Microsystems

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