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AKD4635 Datasheet(PDF) 29 Page - Asahi Kasei Microsystems |
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AKD4635 Datasheet(HTML) 29 Page - Asahi Kasei Microsystems |
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29 / 81 page  [AK4635] Rev. 0.6 2007/10 - 29 - ■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”) A reference clock of PLL is selected among the input clocks to the MCKI, BICK or FCK pin. The required clock to the AK4635 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits. When BICK input frequency is 16fs, the audio interface format supports Mode 0 only (DSP Mode). a) PLL reference clock: MCKI pin BICK and FCK inputs should be synchronized with MCKO output. The phase between MCKO and FCK is not important. MCKO pin outputs the frequency selected by FS3-0 bits (Table 5) AK4635 DSP or μP MCKO BICK FCK SDTO SDTI BCLK FCK SDTI SDTO MCKI 1fs 16fs, 32fs, 64fs 256fs 12MHz, 13.5MHz, 24MHz, 27MHz MCLK Figure 24. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) |
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