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AKD4635 Datasheet(PDF) 78 Page - Asahi Kasei Microsystems |
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AKD4635 Datasheet(HTML) 78 Page - Asahi Kasei Microsystems |
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78 / 81 page  [AK4635] Rev. 0.6 2007/10 - 78 - < MIC differential Input > Top View AVDD NC MCKO Analog Supply 2.8 ∼3.6V 0.1µ 1k Speaker Cp 0.1µ DSP & µP ZD1 VSS1 VSAG VIN PDN CSN VOUT VCOM VCOC FCK CCLK CDTI MPI MICP MICN AOUT MCKI SDTI BICK VSS3 VSS2 DVDD I2C SPP SVDD SPN SDTO Cv Rp + Cs 75 0.1µ + 10µ 0.1µ + 2.2µ 1µ 1µ 220 20 k R2 R1 ZD2 0.1µ Dynamic SPK R1, R2: Short ZD1, ZD2: Open Piezo SPK R1, R2: ≥10Ω ZD1, ZD2: Required 10 1k 1µ Figure 64. Typical Connection Diagram Notes: - VSS1, VSS2 and VSS3 of the AK4635 should be distributed separately from the ground of external controllers. - All digital input pins except pull-down pin should not be left floating. - In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open. - In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 48. - When the AK4635 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”. Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4635. -When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V. Rp and Cp of VCOC pin PLL Lock Time (max) Mode PLL3 bit PLL2 bit PLL1 bit PLL0 bit PLL Reference Clock Input Pin Input Frequency Rp[ Ω] Cp[F ] 0 0 0 0 0 FCK pin 1fs 6.8k 220n 160ms (default) 1 0 0 0 1 BICK pin 16fs 10k 4.7n 2ms 2 0 0 1 0 BICK pin 32fs 10k 4.7n 2ms 3 0 0 1 1 BICK pin 64fs 10k 4.7n 2ms 6 0 1 1 0 MCKI pin 12MHz 10k 4.7n 30ms 7 0 1 1 1 MCKI pin 24MHz 10k 4.7n 30ms 12 1 1 0 0 MCKI pin 13.5MHz 10k 10n 30ms 13 1 1 0 1 MCKI pin 27MHz 10k 10n 30ms Others Others N/A Table 48. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available) |
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