FXLS8971CF datasheet(34/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

SRC_DRDY

Output data-ready event flag

0: A new set of XYZ acceleration and temperature data is not available.

1: A new set of XYZ acceleration and temperature data is available

Notes:

• The SRC_DRDY flag is cleared whenever one or more of the VECM, and OUT_X/Y/Z registers are

read.

• Whenever BUF_CONFIG1[BUF_MODE1:0]] > 00b (buffer enabled), SRC_DRDY is held at logic '0'.

• When BT_MODE=GND, SRC_DRDY bit and the signaled interrupt are cleared whenever one or

more of the VECM, and OUT_X/Y/Z registers are read.

• When BT_MODE=VDD, SRC_DRDY bit is cleared whenever one or more of the VECM, and OUT_

X/Y/Z registers are read. However the data ready interrupt is signaled for TPULSE-MOT seconds (5

ms typ) and it clears itself automatically. The current data ready interrupt pulse is terminated when

the device transitions into STANDBY mode before its completion and therefore may not span for

entire TPULSE-MOT seconds.

SRC_OVF

Output data overflow event flag

0: No overflow condition detected.

1: A new set of XYZ acceleration and temperature output data latches into

OUT_X/Y/Z and TEMP_

OUT registers before the previous set is completely read by the host.

Notes:

• SRC_OVF is not set if at least one of the OUT_X/Y/Z registers was read before the new data set

arrives.

• Whenever the INT_STATUS register is read, SRC_OVF is cleared.

• Whenever BUF_CONFIG1[BUF_MODE[1:0]] > 00b (buffer enabled), SRC_OVF is held at logic '0'.

SRC_BUF

Output data buffer status event flag

0: No output buffer event status flags are active

1: One or more output buffer status event flags are active (BUF_WMRK | BUF_OVF | BUF_

GATE_ERR); reading the

BUF_STATUS register provides more information on the BUF_WMRK

or BUF_OVF event flags that are currently active. Reading the

SYS_MODE register provides

information on the BUF_GATE_ERR flag status.

Notes:

• The SRC_BUF flag is only active when BUF_CONFIG1[BUF_MODE[1:0]] > 00b.

• The BUF_WMRK event flag will not participate in SRC_BUF interrupt generation in triggered mode

(the BUF_WMRK flag is asserted after the buffer is triggered, but it will not signal an external

interrupt as with the other buffer operating modes). If it is required to know when the trigger event

has taken place, the host may use the SDCD or ORIENT interrupts, as appropriate, to indicate

when the buffer is triggered. When the buffer is full, the SRC_BUF flag is set and an external

interrupt is signaled on the INT1 or INT2 pins, if configured.

SRC_SDCD_OT

SDCD outside of thresholds condition event flag (copy of

SDCD_INT_SRC1[OT_EA] flag)

0: SDCD outside of thresholds event is not detected (

SDCD_INT_SRC1[OT_EA] = 0).

1: SDCD outside of thresholds event is detected (

SDCD_INT_SRC1[OT_EA] = 1). The SRC_SDCD_

OT event flag is cleared by reading the

SDCD_INT_SRC1 register when SDCD_CONFIG1[OT_ELE]

= 1, otherwise this flag is cleared automatically by the function when the event condition becomes

false.

SRC_SDCD_WT

SDCD within thresholds condition event flag (copy of

SDCD_INT_SRC2[WT_EA] flag)

0: No SDCD within thresholds event has been detected (

SDCD_INT_SRC2[WT_EA] = 0).

1: An SDCD within thresholds event has been detected (

SDCD_INT_SRC2[WT_EA] = 1). The

SRC_SDCD_WT event flag is cleared by reading the

SDCD_INT_SRC2 register when SDCD_

CONFIG1[WT_ELE] = 1, otherwise the function clears this flag automatically when the event

condition becomes false.

Table 22. INT_STATUS register (address 00h) bit description

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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