FXLS8971CF datasheet(51/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

• The SRC_DRDY event flag is asserted after the specified number of measurements have

completed and the final decimated output result is available. Note that the SRC_DRDY flag is only

asserted when

BUF_CONFIG1[BUF_MODE[1:0]] = 00b

• In LPM, this bit has no effect as the decimation factor is fixed at 1.

WAKE_SDCD_WT

SDCD within thresholds event Auto-WAKE/SLEEP transition source enable

0 (default): SDCD within thresholds event is not used to prevent entry into/trigger an exit from SLEEP

mode.

1: SDCD within thresholds event is used to prevent entry into/trigger an exit from SLEEP mode.

WAKE_SDCD_OT

SDCD outside of thresholds event Auto-WAKE/SLEEP transition source enable

0 (default): SDCD outside of thresholds event is not used to prevent entry into/trigger an exit from

SLEEP mode.

1: SDCD outside of thresholds event is used to prevent entry into/trigger an exit from SLEEP mode.

WAKE_ORIENT

Orientation change event Auto-WAKE/SLEEP transition source enable

0 (default): Orientation change condition is not used as an event to prevent entry into /trigger an exit

from SLEEP mode.

1: Orientation change condition is used as an event to prevent entry into/trigger an exit from SLEEP

mode.

DRDY_PUL

Pulse generation option for DRDY event

0 (default): A SRC_DRDY event is output on the INTx pin as an active high or active low signal

depending on the polarity setting made in INT_POL. The INTx pin remains asserted until the host

reads any of the OUT_X/Y/Z registers.

1: A 32 μs (nominal) duration pulse is output on the configured INTx pin once per ODR cycle. The

output pulse is either positive or negative, depending on the INT_POL setting.

Notes:

• The pulsed output signal is OR'd with all of the other interrupt events assigned to the INTx pin.

• In Motion Detection mode (BT_MODE = VDD), the state of this bit is ignored and has no effect on

device operation.

INT2_FUNC

INT2 output / EXT_TRIG input pin selection

0 (default): INT2/EXT_TRIG pin is configured for the INT2 output function. The logic polarity and

output driver type are specified in the

INT_POL and INT_PP_OD registers. Interrupt signals are

selectively routed to this output pin using the

INT_PIN_SEL register.

1: INT2/EXT_TRIG pin is configured as the EXT_TRIG input function. A positive edge (low-to-high)

transition on the EXT_TRIG pin is used to trigger either a single measurement of the acceleration and

temperature data using the current decimation settings when EXT_TRIG_M = 1 or a single acquisition

of the current acceleration and temperature data when EXT_TRIG_M = 0. This function is useful for

realizing low frequency or asynchronous ODRs initiated by the host system, for example, by using an

MCU timer output pin. When this function is enabled, it is reflected in the

SYS_MODE register.

Notes:

• When the EXT_TRIG function is enabled, any bits set to '1' in the INT_PIN_SEL register (mapping

an event flag to the INT2 output pin) are ignored as the pin becomes a dedicated high-impedance

input pin for the external trigger function.

• The INT2_FUNC bit setting is ignored when BT_MODE = VDD as the external trigger function is not

available in this mode.

INT_PP_OD

INT1 and INT2 pins output driver selection

0 (default): INTx output pin driver is push-pull type.

1: INTx output pin driver is open-drain/open-source type. An external pull-up/pull-down resistor is

required.

Notes:

• If a user operation sets INT_PP_OD before issuing a soft reset command, the setting is maintained

through the reset sequence (only lost when VDD supply is removed or Hibernate mode is enabled).

Table 56. SENS_CONFIG4 register (address 18h) bit description...continued

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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