FXLS8971CF datasheet(79/100 Pages) NXP

79 / 100 page

NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

16 Application information

16.1 System connections

FXLS8971CF connects to a host processor through an I2C or SPI interface. Figure 22 to Figure 27 show the

recommended circuit connections.

16.2 Recommendation for reading data registers

When operating in active mode the sensor stores the acceleration measurement in the associated LSB and

MSB Data registers. Assuming Fast Mode Read is not used, it is important to ensure the coherency between

MSB and LSB data bytes for a given axis when the host MCU reads those two registers, in order words, they

both need to correspond to the same measurement sample.

As mentioned in the registers description, the output data is latched into the OUT_X/Y/Z registers along with the

assertion of the SRC_DRDY event flag. Moreover, when the host MCU initiates a data register read transaction

on the secondary interface (Start condition in I2C mode or SPI_CS transition to low level in SPI mode), the

content of all data registers is locked till the transaction is completed. There are actually shadow registers to

prevent that data registers are updated when a new sample becomes available.

If the MCU performs single byte read transactions, the coherency between MSB and LSB data bytes cannot

be granted as they will be associated to two distinct transactions. Consequently it is highly recommended to

use multiple bytes for data reading, in order to at least collect both MSB and LSB data bytes with a unique read

transaction. Obviously, the MCU can collect all three axes data simultaneously (6 bytes) with a multiple bytes

data reading, and this will also ensure that the XYZ data triplet corresponds to the same timestamp.

Note: This constraint is mostly valid for asynchronous data reading. It is quite lightened if the host MCU

configures the sensor data ready interrupt to perform synchronous (interrupt driven) data reading, as this

provides an adequate trigger to read the samples. The synchronous reading scheme is also recommended to

avoid unnecessary traffic on the secondary interface, such as polling status registers.

Those considerations applies to normal Data output registers OUT_X/Y/Z, but also to BUFF_X/Y/Z registers

and VECM registers.

16.3 Typical application circuits

X7R or X5R ceramic capacitors are recommended for VDD supply decoupling. A 1 µF capacitor in parallel with

a 0.1 µF is recommended as a starting point per the NXP EMC test standard. These capacitors should be

placed as close to the VDD supply pin as practical. The values of the capacitors can be changed to suit the EMC

performance requirements of the application.

aaa-053940

1.0 µF

0.1 µF

VDD

BT_MODE

GND

n.c.

GND

INTF_SEL

INT1/MOT_DET

SPI_CS_B/WAKE_UP

INT2/EXT_TRIG/BOOT_OUT

INT1

WAKE_UP

INT2/EXT_TRIG

SA0/SPI_MISO

I2C_SA0

I2C_SDA

I2C_SCL

SDA/SPI_MOSI

SCL/SCLK

Figure 22. Typical Application Circuit #1 – I2C mode

Notes:

FXLS8971CF

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.1 — 7 March 2024

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