FXLS8971CF datasheet(37/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Field

Description

3 to 0

VECM[11:8]

MSB of the 12-bit unsigned acceleration vector modulus result

Table 27. VECM_MSB register (address 03h) bit description

15.2.5 OUT_X_LSB, OUT_X_MSB, OUT_Y_LSB, OUT_Y_MSB, OUT_Z_LSB, OUT_Z_MSB

registers (addresses 04h to 09h)

These registers contain the 12-bit X-axis, Y-axis, and Z-axis output acceleration data in 2's complement format.

The output data is latched into the

OUT_X/Y/Z registers along with the assertion of the SRC_DRDY event flag.

When

SENS_CONFIG2[F_READ] = 1, the auto-increment mechanism skips the MSB registers in a burst read

transaction. This operation shortens the output data size from 6 bytes to 3 bytes per XYZ sample read.

The byte order of the output data is programmable via

SENS_CONFIG2[LE_BE] and defaults to little-endian

mode.

When

SENS_CONFIG2[F_READ] = 1, the MSB of each axis's data is stored at the LSB address, regardless of

the setting made in

SENS_CONFIG2[LE_BE].

In little-endian mode, the output data registers are arranged with the LSB of each axis's data stored at the lower

address. The upper nibble (MSB) is stored at the next address, in right justified format. In little-endian mode, the

MSB is sign extended to form a 16-bit 2's complement value.

In big-endian mode (

SENS_CONFIG2[LE_BE] = 1), the output data registers are arranged with the MSB of

each axis's data stored at the lower register address. The lower nibble is stored at the next address, and is

left justified. The big-endian option allows a big-endian processor to directly read the output data into an array

without the need to perform byte swaps. The host software must right shift the data by 4 bits (or divide by 16)

in order to obtain the correct scaling of the output data. The sign extension of the data must be done explicitly,

depending on the C compiler used.

Notes:

• There is a ~40 µs delay between the ADC acquisitions of the accelerometer X,Y,Z, and temperature data.

The temperature data is acquired first, followed by the X, Y, and Z axes acceleration data. All data is latched

into the output registers at the same time instant, coincident with the SRC_DRDY event flag being asserted.

Whenever any of the

OUT_X/Y/Z registers is read the SRC_DRDY event flag is cleared.

• SX means sign extension, which is the logic level of the most significant bit of the 12-bit OUT_X/Y/Z register

data, also known as

OUT_X/Y/Z[11].

Bit

Name

OUT_X[7:0]

Reset

—

Access

Table 28. OUT_X_LSB and OUT_X_MSB register (addresses 04h to 05h) with SEN_CONFIG2[LE_BE] = 0 bit

allocation

Bit

Name

OUT_X[11:8]

Reset

—

Access

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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