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FXLS8971CF Datasheet(PDF) 39 Page - NXP Semiconductors

Part # FXLS8971CF
Description  3-Axis Low-g Accelerometer
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8971CF Datasheet(HTML) 39 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8971CF
3-Axis Low-g Accelerometer
Bit
7
6
5
4
3
2
1
0
Name
OUT_Y[11:4]
Reset
—
—
—
—
—
—
—
—
Access
R
R
R
R
R
R
R
R
Table 32. OUT_Y_LSB and OUT_Y_MSB register (addresses 06h to 07h) with SEN_CONFIG2[LE_BE] = 1 bit
allocation
Bit
7
6
5
4
3
2
1
0
Name
OUT_Y[3:0]
0
0
0
0
Reset
—
—
—
—
—
—
—
—
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Name
OUT_Z[11:4]
Reset
—
—
—
—
—
—
—
—
Access
R
R
R
R
R
R
R
R
Table 33. OUT_Z_LSB and OUT_Z_MSB register (addresses 08h to 09h) with SEN_CONFIG2[LE_BE] = 1 bit
allocation
Bit
7
6
5
4
3
2
1
0
Name
OUT_Z[3:0]
0
0
0
0
Reset
—
—
—
—
—
—
—
—
Access
R
R
R
R
R
R
R
R
15.2.6 BUF_STATUS register (address 0Bh)
The content stored at this register address depends on whether the output data buffer is enabled or not. When
BUF_CONFIG1[BUF_MODE[1:0]] = 00b, the output data buffer is disabled and this register always contains the
value 00h.
When
BUF_CONFIG1[BUF_MODE[1:0]] > 00b, the BUF_STATUS register content as shown in Table 34 and
Table 35.
Bit
7
6
5
4
3
2
1
0
Name
BUF_
WMRK
BUF_OVF
BUF_CNT[5:0]
Reset
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Table 34. BUF_STATUS register (address 0Bh) bit allocation
FXLS8971CF
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 2.1 — 7 March 2024
39 / 100



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