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FXLS8971CF Datasheet(PDF) 77 Page - NXP Semiconductors

Part # FXLS8971CF
Description  3-Axis Low-g Accelerometer
PDF  100 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8971CF Datasheet(HTML) 77 Page - NXP Semiconductors

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NXP Semiconductors
FXLS8971CF
3-Axis Low-g Accelerometer
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
SDCD_UTHS[11:8]
Reset (BT_MODE = GND)
0
0
0
0
0
0
0
0
Reset (BT_MODE = VDD)
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 114. SDCD_UTHS_MSB register (address 36h) bit allocation
Field
Description
3 to 0
SDCD_UTHS[11:8]
MSB (nibble) of the signed 12-bit 2's complement upper-threshold value
Table 115. SDCD_UTHS_MSB register (address 36h) bit description
15.6 Self-test configuration registers
15.6.1 SELF_TEST_CONFIG1 register (address 37h)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
ST_IDLE[4:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 116. SELF_TEST_CONFIG1 register (address 37h) bit allocation
Field
Description
4 to 0
ST_IDLE
Self-Test Idle phase duration:
The value contained in ST_IDLE determines the Self-Test Idle phase duration per Equation 3.
(3)
Table 117. SELF_TEST_CONFIG1 register (address 37h) bit description
15.6.2 SELF_TEST_CONFIG2 register (address 38h)
Bit
7
6
5
4
3
2
1
0
Name
—
—
—
—
ST_DEC[3:0]
Reset
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 118. SELF_TEST_CONFIG2 register (address 38h) bit allocation
Field
Description
3 to 0
Self-Test measurement phase decimation factor
Table 119. SELF_TEST_CONFIG2 register (address 38h) bit description
FXLS8971CF
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 2.1 — 7 March 2024
77 / 100



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