FXLS8971CF datasheet(70/100 Pages) NXP

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NXP Semiconductors

FXLS8971CF

3-Axis Low-g Accelerometer

Bit

Name

WT_EA

—

X_WT_EF

—

Y_WT_EF

—

Z_WT_EF

—

Reset

Access

Table 98. SDCD_INT_SRC2 register (address 2Eh) bit allocation

Field

Description

WT_EA

SDCD within-thresholds event active flag

0 (default): Event flag has not been asserted; none of the input data (absolute mode) or deltas

(relative mode) for the enabled axes is within the window defined by the

SDCD_UTHS and SDCD_

LTHS registers.

1: All, or at least one of, (depending on the LOGIC function selected in

SDCD_CONFIG2[WT_LOG_

SEL

]) the enabled axes sensor data (absolute mode) or deltas (relative mode) sits within both the

upper and lower thresholds specified in the

SDCD_UTHS and SDCD_LTHS registers (for example,

SDCD_LTHS, and < SDCD_UTHS). This flag is set whenever the condition is true for a number of

ODR cycles ≥

SDCD_WT_DBCNT.

Notes:

• The axes selected for participation in the within thresholds condition evaluation are enabled via the

X/Y/Z_WT_EN bits in the

SDCD_CONFIG1 register. The logic mode for the function is set in the

SDCD_CONFIG2 register. If none of the X/Y/Z_WT_EN bits are set then the SDCD_WT function is

effectively disabled.

• When SENS_CONFIG4[WAKE_SDCD_WT] = 1, the Auto-WAKE/SLEEP timer is reset on every

ODR cycle when the WT_EA flag is asserted (set), which prevents the device from transitioning

into SLEEP mode. This flag must be de-asserted (cleared) in order for FXLS8971CF to transition to

SLEEP mode.

X_WT_EF

X-axis data or delta inside of upper and lower thresholds event flag; This flag is only valid if

X_WT_EN = 1:

0: X-axis data or delta is ≥

SDCD_UTHS value or ≤ SDCD_LTHS value.

1: X-axis data or delta is <

SDCD_UTHS and > SDCD_LTHS value.

Notes:

• The SDCD_CONFIG1[WT_ELE] bit determines the behavior of this bit. If WT_ELE = 1, the flag

is latched when WT_EA goes high, and remains set until it is cleared by reading the

SDCD_

INT_SRC2 register. If the host wishes to know the state of this event flag, it must be read prior to

reading the

SDCD_INT_SRC2 register.

• If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated if WT_EA = 1 and the SDCD_WT_DBCNT

value is reached. If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated even if WT_EA = 0 when the

SDCD_WT_DBCNT value is set to 0.

Y_WT_EF

Y-axis data or delta inside of upper and lower thresholds event flag; This flag is only valid if

Y_WT_EN = 1:

0: Y-axis data or delta is ≥

SDCD_UTHS value or ≤ SDCD_LTHS value.

1: Y-axis data or delta is <

SDCD_UTHS and > SDCD_LTHS value.

Notes:

• The SDCD_CONFIG1[WT_ELE] bit determines the behavior of this bit. If WT_ELE = 1, the flag

is latched when WT_EA goes high, and remains set until it is cleared by reading the

SDCD_

INT_SRC2 register. If the host wishes to know the state of this event flag, it must be read prior to

reading the

SDCD_INT_SRC2 register.

• If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated if WT_EA = 1 and the SDCD_WT_DBCNT

value is reached. If WT_ELE = 0, the X/Y/Z_WT_EF flags are updated even if WT_EA = 0 when the

SDCD_WT_DBCNT value is set to 0.

Table 99. SDCD_INT_SRC2 register (address 2Eh) bit description

FXLS8971CF

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Product data sheet

Rev. 2.1 — 7 March 2024

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