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FXLS8971CF Datasheet(PDF) 56 Page - NXP Semiconductors |
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FXLS8971CF Datasheet(HTML) 56 Page - NXP Semiconductors |
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56 / 100 page ![]() NXP Semiconductors FXLS8971CF 3-Axis Low-g Accelerometer WAKE mode ODR (Hz) WAKE mode ODR Period (ms) ASLP_COUNT Period (ms) Max Inactivity Times 3200 0.3125 0.3125 1.28 1600 0.625 0.625 2.56 800 1.25 1.25 5.12 400 2.5 2.5 10.24 200 5 5 20.48 100 10 10 40.96 50 20 20 81.92 25 40 40 163.84 12.5 80 80 327.68 6.25 160 160 655.36 3.125 320 320 1310.72 1.563 640 640 2621.44 0.781 1280 1280 5242.54 Table 69. ASLP_COUNT timer period Interrupt Event Source Event flag can clear auto-sleep timer? Event flag can transition the device from SLEEP to WAKE mode? SRC_DRDY No No SRC_OVF No No SRC_BUF Yes[1] No SRC_SDCD_OT Yes Yes SRC_SDCD_WT Yes Yes SRC_ORIENT Yes Yes SRC_ASLP No[2] No[2] SRC_BOOT No No Table 70. Auto-WAKE/SLEEP Interrupt Event Sources [1] When BUF_CONFIG2[WAKE_SRC_BUF] = 1, clearing the SRC_BUF event flag resets the auto-sleep timer and prevent FXLS8971CF from entering SLEEP mode. When BUF_CONFIG2[WAKE_SRC_BUF] = 0 (default), FXLS8971CF enters SLEEP mode regardless of the state of the BUF_WMRK or BUF_OVF event flags. [2] If the BUF_GATE bit is set to logic '1', it prevents the output buffer from accepting new data after a WAKE-to-SLEEP or SLEEP-to-WAKE operating mode transition until the host first empties the buffer contents. The BUF_GATE bit is useful for preventing acceleration data from different WAKE and SLEEP mode ODRs from being mixed within the buffer. 15.3.11 INT_EN register (address 20h) This register is used to enable and disable the various interrupt event generators embedded within the device. Note: • When BT_MODE = VDD, the INT1/MOT_DET pin signals any mapped (and enabled) interrupts with a TPULSE- MOT ms active low pulse (open-drain output with external pull-up). • Any enabled interrupt is signaled with a TPULSE-MOT ms pulse at the ODR rate until the respective interrupt source flag is cleared. FXLS8971CF All information provided in this document is subject to legal disclaimers. © 2024 NXP B.V. All rights reserved. Product data sheet Rev. 2.1 — 7 March 2024 56 / 100 |
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