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ADS8513

SLAS486 – JUNE 2007

DEVICE INFORMATION (continued)

Terminal Functions

TERMINAL

DIGITAL I/O

DESCRIPTION

NAME

SO NO.

1

Analog Input. See Table 1 and Table 3.

3

Analog Input. See Table 1 and Table 3.

4

Analog Input. See Table 1 and Table 3.

BUF

5

Reference buffer output. Connect to R1IN, R2IN, or R3IN as needed

CAP

6

Reference buffer compensationnode. Decouple to ground with a 1-

μF tantalum capacitor in

parallel with a 0.01-

μF ceramic capacitor.

REF

7

Reference input/output. Outputs internal 2.5-V reference via a series 4-k

Ω resisitor.

Decouple this voltage with a 1-

μF to 2.2-μF tantalum capacitor to ground. If an external

reference voltage is applied to this pin, it will override the internal reference.

DGND

14

Digital ground

DATACLK

9

I/O

Data clock pin. With EXT/INT low, this pin is an output and provides the synchrnous clock

for the serial data. The output is 3-stated when CS is high. With EXT/INT high, this pin is an

input and the serial data clock must be provided externally.

DATA

10

O

Serial data output. The serial data is always the result of the last completed conversion and

is synchronized to DATACLK. If DATACLK is from the internal clock (EXT/INT low), the

serial data is valid on both the rising and falling edges of DATACLK. Data is 3-stated when

CS is high.

EXT/INT

11

I

External/Internal DATACLK pin. Selects the source of the synchronous clock for serial data.

if high, the clock must be provided externally. If low, the clock is derived from the internal

conversion clock. Note that the clock used to time the conversion is always internal

regardless of the status of EXT/INT.

CONV

12

Convert input. A faaling edge on this input puts the internal sample/hold into the hold state

and starts a conversion regardless of the state of CS. If a conversion is already in progress,

the falling edge is ignored. If EXT/INT is low, data from the previous conversion will be

serially transmitted during the current conversion.

CS

13

I

Chip select. This input 3-states all outputs when high and enables all outputs when low.

This includes DATA, BUSY, and DATACLK (when EXT/INT is low). Note that a falling edge

on CONV will initiate a conversion even when CS is high.

BUSY

14

O

Busy output. When a conversion is started, BUSY goes low and remains low throughout the

conversion. If EXT/INT is low, data is serially transmitted while BUSY is low. BUSY is

3-stated when CS is high.

PWRD

15

I

Power down input. When high, the majority of the ADS851 is placed in a low power mode

and power consumption is significantly reduced. CONV must be taken low prior to PWRD

going low in order to achieve the lowest power consumption. The time required for the

ADS8513 to return to normal operation after power down depends on a number of factors.

Consult the POWER DOWN section for more information.

GND

2, 8

Ground.

16

+5-V Supply input. For best performance, decouple to ground with a 0.1-

μF ceramic

capacitor in parallel with a 10-

μF tantalum capacitor.

Table 1. Input Ranges

ANALOG INPUT

INPUT IMPEDANCE

RANGE

±10 V

BUF

GND

45.7 k

Ω

0.3125V to

> 10,000

2.8125 V

±5 V

GND

BUF

26.7 k

Ω

0 V to 10 V

BUF

GND

26.7 k

Ω

0 V to 4 V

BUF

GND

21.3

±3.33 V

BUF

21.3

0.5 V to 4.5 V

GND

GND

21.3

Copyright © 2007, Texas Instruments Incorporated

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