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STARTING A CONVERSION

ADS8513

SLAS486 – JUNE 2007

BASIC OPERATION (continued)

If a conversion is not currently in progress, a falling edge on the CONV input places the sample and hold into the

hold mode and begins a conversion, as shown in Figure 3 and with the timing given in Table 2. During the

conversion, the CONV input is ignored. Starting a conversion does not depend on the state of CS. A conversion

can be started once every 25

μs (40-kHz maximum conversion rate). There is no minimum conversion rate.

Even though the CONV input is ignored while a conversion is in progress, this input should be held static during

the conversion period. Transitions on this digital input can easily couple into sensitive analog portions of the

converter, adversely affecting the conversion results (see the Sensitivity to External Digital Signals section of this

data sheet for more information).

Ideally, the CONV input should go LOW and remain LOW throughout the conversion. It should return HIGH

sometime after BUSY goes HIGH. In addition, it should be HIGH prior to the start of the next conversion for a

signal that is acquired for the next conversion.

An acceptable alternative is to return the CONV input HIGH as soon after the start of the conversion as possible.

For example, a negative going pulse 100ns wide would make a good CONV input signal. It is strongly

static (either HIGH or LOW). During this time, the converter is more sensitive to external noise.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

Conversion Plus Acquisition Time

25

μs

CONV LOW to All Digital Inputs Stable

19

μs

CONV LOW to Initiate a Conversion

0.04

12

μs

BUSY Rising to Any Digital Input Active

5

ns

CONV HIGH Prior to Start of Conversion (CONV high time)

15

ns

BUSY LOW

18

20

μs

CONV LOW to BUSY LOW

12

20

ns

Aperture Delay (CONV falling edge to actual conversion start)

5

ns

Conversion Time

18

20

μs

Conversion Complete to BUSY Rising

90

ns

Acquisition Time

5

μs

CONV LOW to Rising Edge of First Internal DATACLK

0.27

μs

Internal DATACLK HIGH

300

410

425

ns

Internal DATACLK LOW

300

410

425

ns

Internal DATACLK Period

0.6

0.82

0.85

μs

DATA Valid to Internal DATACLK Rising

15

35

ns

Internal DATACLK Falling to DATA Not Valid

22

37

ns

Falling Edge of Last DATACLK to BUSY Rising

1

μs

External DATACLK Rising to DATA Not Valid

4

14

ns

External DATACLK Rising to DATA Valid

2

12

20

ns

External DATACLK HIGH

15

ns

External DATACLK LOW

15

ns

External DATACLK Period

35

ns

CONV LOW to External DATACLK Active

15

ns

External DATACLK LOW or CS HIGH to BUSY Rising

1

μs

CS LOW to Digital Outputs Enabled

15

ns

CS HIGH to Digital Outputs Disabled

15

ns

Copyright © 2007, Texas Instruments Incorporated

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