www.ti.com

Q

D

S0

Q

Updateoftheshift

registeroccursjustprior

D

S1

Q

D

S2

Q

D

S14

Q

D

S15

Q

ShiftRegister

WorkingRegister

ConverterCore

D

SOUT

Q

D

W0

Q

Eachflip-flopinthe

workingregisteris

latchedasthe

conversionproceeds

D

W1

Q

D

W2

Q

D

W14

Q

D

W15

• • •

Delay

DATA

BUSY

DATACLK

CDAC

ControlLogic

Clock

REF

EXT/INT

CONV

CS

NOTE:(1)IfEXT/INT isHIGH(externalclock),DATACLKisHIGH,andCSisLOWdu ring

thistime,theshiftregisterwillnotbeupdatedandtheconversionresultwill belost.

CONV

t

t

25

BUSY

NOTE:Updateoftheinternalshiftregisteroccursinthe

shadedregion.IfEXT/INT isHIGH,thenDATACLK

mustbeLOWorCSmustbeHIGHduringthistime.

READING DATA

ADS8513

SLAS486 – JUNE 2007

Figure 4. Block Diagram of the ADS8513 Digital Inputs and Outputs

Figure 5. Timing of the Shift Register Update

The ADS8513 digital output is in Binary Two’s Complement (BTC) format. Table 3 shows the relationship

between the digital output word and the analog input voltage under ideal conditions.

Copyright © 2007, Texas Instruments Incorporated

Submit Documentation Feedback

9

Product Folder Link(s): ADS8513