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SIGNAL CONDITIONING

SENSITIVITY TO EXTERNAL DIGITAL SIGNALS

ADS8513

SLAS486 – JUNE 2007

LAYOUT (continued)

All the ground pins of the A/D converter should be tied to an analog ground plane, separated from the system's

digital logic ground, to achieve optimum performance. Both analog and digital ground planes should be tied to

the system ground as near to the power supplies as possible. This helps to prevent dynamic digital ground

currents from modulating the analog ground through a common impedance to power ground.

The FET switches used for the sample hold on many CMOS A/D converters release a significant amount of

charge injection which can cause the driving op amp to oscillate. The amount of charge injection due to the

sampling FET switch on the ADS8507 is approximately 5% to 10% of the amount on similar A/D converters with

the charge redistribution digital-to-analog converter (DAC) CDAC architecture. There is also a resistive front end

which attenuates any charge which is released. The end result is a minimal requirement for the drive capability

on the signal conditioning preceding the A/D converter. Any op amp sufficient for the signal in an application will

be sufficient to drive the ADS8507.

The resistive front end of the ADS8507 also provides a specified ±25-V overvoltage protection. In most cases,

this eliminates the need for external over-voltage protection circuitry.

All successive approximation register-based A/D converters are sensitive to external sources of noise. The

reason for this will be explained in the following paragraphs. For the ADS8513 and similar A/D converters, this

noise most often originates due to the transition of external digital signals. While digital signals that run near the

converter can be the source of the noise, the biggest problem occurs with the digital inputs to the converter itself.

In many cases, the system designer may not be aware that there is a problem or a potential for a problem. For a

12-bit system, these problems typically occur at the least significant bits and only at certain places in the

converter’s transfer function. For a 16-bit converter, the problem can be much easier to spot.

For example, the timing diagram in Figure 3 shows that the CONV signal should return HIGH sometime during

transition of the CONV signal has the potential of creating a good deal of noise on the ADS8513 die. If this

transition occurs at just precisely the wrong time, the conversion results could be affected. In a similar manner,

transitions on the DATACLK input could affect the conversion result.

For the ADS8513, there are 16 separate bit decisions which are made during the conversion. The most

significant bit decision is made first, proceeding to the least significant bit at the end of the conversion. Each bit

decision involves the assumption that the bit being tested should be set. This is combined with the result that has

been achieved so far. The converter compares this combined result with the actual input voltage. If the combined

result is too high, the bit is cleared. If the result is equal to or lower than the actual input voltage, the bit remains

HIGH. This is why the basic architecture is referred to as successive approximation register (SAR).

If the result so far is getting very close to the actual input voltage, then the comparison involves two voltages

which are very close together. The ADS8513 has been designed so that the internal noise sources are at a

minimum just prior to the comparator result being latched. However, if an external digital signal transitions at this

time, a great deal of noise will be coupled into the sensitive analog section of the ADS8513. Even if this noise

produces a difference between the two voltages of only 2 mV, the conversion result will be off by 52 counts or

least significant bits (LSBs). (The internal LSB size of the ADS8513 is 38

μV regardless of the input range.)

Once a digital transition has caused the comparator to make a wrong bit decision, the decision cannot be

corrected (unless some type of error correction is employed). All subsequent bit decisions will then be wrong.

Figure 15 shows a successive approximation process that has gone wrong. The dashed line represents what the

correct bit decisions should have been. The solid line represents the actual result of the conversion.

Keep in mind that the time period when the comparator is most sensitive to noise is fairly small. Also, the peak

portion of the noise event produced by a digital transition is fairly brief, as most digital signals transition in a few

nanoseconds. The subsequent noise may last for a period of time longer than this and may induce further effects

which require a longer settling time. However, in general, the event is over within a few tens of nanoseconds.

Copyright © 2007, Texas Instruments Incorporated

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