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INTERNAL DATACLK

t

17

DATACLK

BUSY

CONV

t

1

t

12

t

18

t

16

t

14

t

13

t

15

1

1

2

3

14

15

16

DATA

MSB

Bit14

Bit13

Bit2

Bit1

LSB

MSB

EXTERNAL DATACLK

ADS8513

SLAS486 – JUNE 2007

Figure 5 shows the relationship between the various digital inputs, digital outputs, and internal logic of the

ADS8513. Figure 6 shows when the internal shift register of the ADS8513 is updated and how this relates to a

single conversion cycle. Together, these two figures point out a very important aspect of the ADS8513: the

conversion result is not available until after the conversion is complete. The implications of this are discussed in

the following sections.

With EXT/INT tied LOW, the result from conversion ‘n’ is serially transmitted during conversion ‘n+1’, as shown in

Figure 4 and with the timing given in Table 2. Serial transmission of data occurs only during a conversion. When

a transmission is not in progress, DATA and DATACLK are LOW.

During the conversion, the results of the previous conversion will be transmitted via DATA, while DATACLK

provides the synchronous clock for the serial data. The data format is 16-bit, Binary Two’s Complement, and

MSB first. Each data bit is valid on both the rising and falling edges of DATACLK. BUSY is LOW during the entire

serial transmission and can be used as a frame synchronization signal.

Figure 6. Serial Data Timing, Internal Clock (EXT/INT and CS Low)

With EXT/INT tied HIGH, the result from conversion ‘n’ is clocked out after the conversion has completed, during

the next conversion (‘n+1’), or a combination of these two. Figure 7 shows the case of reading the conversion

result after the conversion is complete. Figure 8 describes reading the result during the next conversion. Figure 9

combines the important aspects of Figure 7 and Figure 8 as to reading part of the result after the conversion is

complete and the remainder during the next conversion.

The serial transmission of the conversion result is initiated by a rising edge on DATACLK. The data format is

16-bit, Binary Two’s Complement, and MSB first. Each data bit is valid on the falling edge of DATACLK. In some

cases, it might be possible to use the rising edge of the DATACLK signal. However, one extra clock period (not

shown in Figure 7, Figure 8), and Figure 9 is needed for the final bit.

and Figure 9). If this is not observed during this time, the output shift register of the ADS8513 will not be updated

with the conversion result. Instead, the previous contents of the shift register will remain and the new result will

be lost.

Before reading the next three paragraphs, consult the Sensitivity to External Digital Signals section of this data

sheet. This will explain many of the concerns regarding how and when to apply the external DATACLK signal.

EXTERNAL DATACLK ACTIVE AFTER THE CONVERSION

The preferred method of obtaining the conversion result is to provide the DATACLK signal after the conversion

has been completed and before the next conversion starts—as shown in Figure 7. Note that the DATACLK signal

should be static before the start of the next conversion. If this is not observed, the DATACLK signal could affect

the voltage that is acquired.

10

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