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BUSY

CONV

t

1

t

5

DATACLK

t

4

t

23

t

22

t

21

t

20

t

19

1

2

3

4

14

15

16

DATA

MSB

Bit14

Bit13

Bit2

Bit1

LSB

3

4

BUSY

CONV

t

2

t

1

DATACLK

t

24

t

25

t

23

t

22

t

21

t

20

t

19

1

1

2

15

16

DATA

MSB

Bit14

Bit13

Bit1

LSB

MSB

ADS8513

SLAS486 – JUNE 2007

Figure 7. Serial Data Timing, External Clock, Clocking After the Conversion Completes (EXT/INT High, CS

Low)

EXTERNAL DATACLK ACTIVE DURING THE NEXT CONVERSION

Another method of obtaining the conversion result is shown in Figure 8. Since the output shift register is not

updated until the end of the conversion, the previous result remains valid during the next conversion. If a fast

clock (

from the DATACLK signal is less likely to affect the conversion result.

Figure 8. Serial Data Timing, External Clock, Clocking During the Next Conversion (EXT/INT High, CS

Low)

EXTERNAL DATACLK ACTIVE AFTER THE CONVERSION AND DURING THE NEXT CONVERSION

Figure 9 shows a method that is a hybrid of the two previous approaches. This method works very well for

microcontrollers that do serial transfers 8 bits at a time and for slower microcontrollers. For example, if the fastest

serial clock that the microcontroller can produce is 1

μs, the approach shown in Figure 7 would result in a

diminished throughput (26-kHz maximum conversion rate). The method described in Figure 8 could not be used

Figure 9 results in an improved throughput rate (33 kHz maximum with a 1-

μs clock) and DATACLK is not active

Copyright © 2007, Texas Instruments Incorporated

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