TMPR4956C datasheet(166/286 Pages) TOSHIBA

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Chapter 10 Clock Interface

10-2

10.2 Basic System Clocks

The various clock signals used in the TX4956 processor are described below, starting with MasterClock,

upon which the processor bases all internal and external clocking.

The clocks on the TX4956 processor are controlled by an on-processor Phase-locked Loop (PLL) circuit.

This circuit keeps the TX4956 processor’s internal clock edges aligned with the clock edges of the

MasterClock signal, which itself acts as the master system clock.

Inside the TX4956 processor, the MasterClock signal can be multiplied by a factor set by the DivMode[2:0]

inputs to the processor. All internal clocks are then derived from this clock. The TX4956 processor has two

primary internal clocks, the pipeline (also referred to as processor) clock, CPUCLK, and the system interface

clock, GBUSCLK. GBUSCLK has the same frequency and phase as MasterClock.

10.2.1

MasterClock

The Processor bases all internal and external clocking on the single MasterClock input signal.

MasterClock specifications are shown in Figure 10.2.1.

Figure 10.2.1 MasterClock

10.2.2

CPUCLK

The pipeline (or processor) clock, CPUCLK, can be 1:2, 1:2.5, 1:3, 1:3.5, 1:4, 1:4.5, 1:5, 1:6 times the

MasterClock frequency. This multiplication factor is determined by DivMode[2:0] pins, which are static

signal inputs to TX4956.

All internal registers and latches use CPUCLK.

10.2.3

GBUSCLK

The system interface clock, GBUSCLK, is the same as the MasterClock frequency. GBUSCLK is

always derived from CPUCLK. The TX4956 processor drives its outputs on this clock edge.

The first rising edge of GBUSCLK, after ColdReset* is deasserted, is aligned with the first rising edge

of MasterClock.

tMCF

tMCR

tMCH

tMCL

tMCP

0.8VCC IO

0.2VCC IO

tMCH

1.5 V

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