TMPR4956C datasheet(162/286 Pages) TOSHIBA

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Chapter 9 Initialization Interface

9-4

9.2.3

Soft Reset

A soft reset is used to reset the processor without affecting the clocks; in other words, a soft reset is a

logic reset.

Asserting the Reset* signal resets the processor without disrupting the clocks and allows the

processor to retain as much of its state as possible for debugging. (For information on saving the

processor states, see the section on SoftReset exception in CPU Exception Processing.) Because

asserting the Reset* signal results in an immediate soft reset, multicycle instructions such as cache

misses or floating-point instructions may be aborted and some data lost as a result.

A soft reset is started by assertion of the Reset* signal. Reset* signal must be asserted for a minimum

of 16 cycles, and must be asserted and deasserted synchronously with MasterClock. In general, data in

the processor is preserved for debugging purposes.

While Reset* signal is asserted, the processor assumes bus ownership and drives the SysAD bus, as

follows:

In R5000 Mode

In R4300 Mode

SysAD:

64'hxxxxxxxxxxxxxxxx (unknown output)

SysCmd:

9'b111010000 (output)

ValidOut*:

1'b1 (output)

Release*:

1'b1 (output)

After Reset* signal is deasserted, the processor branches to the Reset Exception vector and begins

executing the SoftReset Exception handler. Information about the CPU register bits by a soft reset is

provided in the Section 8.5, “SoftReset Exception.”

When Reset* signal is asserted during a SysAD transfer, all external agents must be reset to avoid bus

contention on the SysAD bus. Figure 9.2.3 illustrates the soft reset timing.

Figure 9.2.3 Soft Reset

MasterClock

(MClk)

ColdReset*

Wavy lines indicate one or more identical cycles, not

shown due to space constraints.

TDH

TDS

Reset*

≥ 16MClk cycles

VCC

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