TMPR4956C datasheet(161/286 Pages) TOSHIBA

161 / 286 page

Chapter 9 Initialization Interface

9-3

9.2.2

Cold Reset

A cold reset is used to completely reset the processor, including the processor clock. Processor states

should be saved as follows.

After the processor power has stabilized, ColdReset* must be kept asserted for a minimum of 64,000,

MasterClock cycles to ensure that the processor clock locks with respect to the MasterClock input.

ColdReset* may be asserted and deasserted asynchronously from the rising edge of MasterClock.

While ColdReset* is asserted, the processor assumes bus ownership and drives the SysAD bus, as

follows:

In R5000 Mode

In R4300 Mode

SysAD:

64’hxxxxxxxxxxxxxxxx (unknown output)

64’hxxxxxxxxxxxxxxxx

(unknown

output)

SysCmd:

9’b111010000 (output)

ValidOut*:

1’b1 (output)

Release*:

1’b1 (output)

After ColdReset* is deasserted, the processor branches to the Reset Exception vector and begins

executing the ColdReset Exception handler. Information about the CPU register bits during a cold reset

is provided in the Chapter 3, “TX49 Core’s Registers.”

When ColdReset* is asserted during a SysAD transfer, all external agents must be reset to avoid bus

contention on the SysAD bus. Figure 9.2.2 illustrates the cold reset timing.

Figure 9.2.2 Cold Reset

VCC

MasterClock

(MClk)

ColdReset*

Wavy lines indicate one or more identical cycles, not

shown due to space constraints.

≥ 64,000MClk cycles

TDH

TDS

Reset*

≥ 16MClk cycles

TMPR4956C Datasheet(PDF) 161 Page - Toshiba Semiconductor