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TMPR4956C Datasheet(PDF) 158 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4956C Datasheet(HTML) 158 Page - Toshiba Semiconductor

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Chapter 8 CPU Exception
8-30
8.21.6
Saving and Restoring State
Sixteen doubleword
† coprocessor load or store operations save or restore the coprocessor floating-point
register state in memory. The remainder of control and status information can be saved or restored
through CFC1/CTC1 instructions, and saving and restoring the processor registers. Normally, the
Control/Status
register is saved first and restored last.
When state is restored, state information in the Control/Status register indicates the exceptions that are
pending. Writing a zero value to the Cause field of Control/Status register clears all pending exceptions,
permitting normal processing to restart after the floating-point register state is restored.
8.21.7
Trap Handlers for IEEE Standard 754 Exceptions
The IEEE Standard 754 strongly recommends that users be allowed to specify a trap handler for any of
the five standard exceptions that can compute; the trap handler can either compute or specify a substitute
result to be placed in the destination register of the operation.
By retrieving an instruction using the processor Exception Program Counter (EPC) register, the trap
handler determines:
•
exceptions occurring during the operation
•
the operation being performed
•
the destination format
On Overflow or Underflow exceptions (except for conversions), and on Inexact exceptions, the trap
handler gains access to the correctly rounded result by examining source registers and simulating the
operation in software.
On Overflow or Underflow exceptions encountered on floating-point conversions, and on Invalid
Operation and Divide-by-Zero exceptions, the trap handler gains access to the operand values by
examining the source registers of the instruction.
The IEEE Standard 754 recommends that, if enabled, the overflow and underflow traps take
precedence over a separate inexact trap. This prioritization is accomplished in software; hardware sets the
bits for both the Inexact exception and the Overflow or Underflow exception.
† 32 doublewords if the FR bit is set to 1.



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