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TMPR4956C Datasheet(PDF) 154 Page - Toshiba Semiconductor

Part # TMPR4956C
Description  64-Bit TX System RISC TX49 Family
PDF  286 Pages
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Manufacturer  TOSHIBA [Toshiba Semiconductor]
Direct Link  http://www.semicon.toshiba.co.jp/eng
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TMPR4956C Datasheet(HTML) 154 Page - Toshiba Semiconductor

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Chapter 8 CPU Exception
8-26
8.21.3
Exception Trap Processing
When a floating-point exception trap is taken, the Cause register indicates the floating-point
coprocessor is the cause of the exception trap.
The Floating-Point Exception (FPE) code is used, and the Cause bits of the floating-point
Control/Status register indicate the reason for the floating-point exception. These bits are, in effect, an
extension of the system coprocessor Cause register.
8.21.4
Flags
A Flag bit is provided for each IEEE exception. This Flag bit is set to a 1 on the assertion of its
corresponding exception, with no corresponding exception trap signaled.
When no exception trap is signaled, floating-point coprocessor takes a default action, providing a
substitute value for the exception-causing result of the floating-point operation. The particular default
action taken depends upon the type of exception. Table 8.21.1 lists the default action taken by the FPU for
each of the IEEE exceptions.
Table 8.21.1 Default FPU Exception Actions
Field
Description
Rounding
Mode
Default Action
I
Inexact exception
ANY
Supply a rounded result.
U
Underflow
exception
ANY
Supply a rounded result.
O
Overflow
exception
RN
Modify overflow values to
∞ with the sign of the
intermediate result.
RZ
Modify overflow values to the format’s largest finite
number with the sign of the intermediate result.
RP
Modify negative overflows to the format’s most negative
finite number; modify positive overflows to +
∞
RM
Modify positive overflows to the format’s largest finite
number; modify negative overflows to –
∞
Z
Division by zero
ANY
Supply a properly signed
∞
V
Invalid operation
ANY
Supply a quiet Not a Number (NaN).
The FPU detects the eight exception causes internally. When the FPU encounters one of these unusual
situations, it causes either an IEEE exception or an Unimplemented Operation exception (E).
Table 8.21.2 lists the exception-causing situations and contrasts the behavior of the FPU with the
requirements of the IEEE Standard 754.



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