TMPR4956C datasheet(151/286 Pages) TOSHIBA

Part #	TMPR4956C

Description	64-Bit TX System RISC TX49 Family

PDF	286 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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151 / 286 page

Chapter 8 CPU Exception

8-23

Figure 8.20.4 TLB/XTLB Miss Exception Servicing Guidelines (SW)

ERET

Service Code

MFC0 -

CONTEXT

Comments

* ERET is not allowed in the branch delay slot of

another Jump Instruction

* Processor does not execute the instruction which is

in the ERET’s branch delay slot

* PC

← EPC; EXL = 0

* LLbit

← 0

* Load the mapping of the virtual address in Context Reg.

Move it to ENLO and Write into the TLB

* There could be a TLB miss again during the mapping

of the data or instruction address. The processor will

jump to the general exception vector since the EXL is 1.

(Option to complete the first level refill in the general

exception handler or ERET to the original instruction

and take the exception again)

* Unmapped vector TLBMod, TLBInv,

TLB Refill exceptions not possible

* EXL

= 1 so Interrupt exceptions disabled

* OS/System to avoid all other exceptions

* Only Cold Reset, Soft Reset, NMI exceptions

possible.

TMPR4956C Datasheet(PDF) 151 Page - Toshiba Semiconductor