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TMPR4956C Datasheet(PDF) 150 Page - Toshiba Semiconductor |
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TMPR4956C Datasheet(HTML) 150 Page - Toshiba Semiconductor |
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150 / 286 page  Chapter 8 CPU Exception 8-22 Figure 8.20.3 TLB/XTLB Miss Exception Handler (HW) Vector Offset = 0x180 Vector Offset = 0x000 Vector Offset = 0x080 EXL ← 1 EnHi ← VPN2, ASID X/Context ← VPN2 Set Cause Reg. ExcCode, CE and Set BadVA EnHi ← VPN2, ASID X/Context ← VPN2 Set Cause Reg. ExcCode, CE and Set BadVA To TLB/XTLB Exception Servicing Guidelines Instr. in Br. Dly. Slot? EXL (SR bit 1) EXL (SR bit 1) XTLB Exception? EPC ← PC Cause bit 31 (BD) ← 0 EPC ← (PC-4) Cause bit 31 (BD) ← 1 BEV (SR bit 22) PC ← 0xFFFF FFFF 8000 0000 + Vec. Off. (unmapped, cached) PC ← 0xFFFF FFFF BF00 0200 + Vec. Off. (unmapped, uncached) = 0 (normal) = 1 (bootstrap) Processor forced to Kernel Mode & interrupt disabled No Yes Points to General Exception Points to Refill Exception No Yes = 0 = 0 = 1 = 1 Check if exception within another exception |
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