TMPR4956C datasheet(147/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-19

8.19 Interrupt Exception

8.19.1

Cause

The Interrupt exception is raised by any of eight interrupts (two software and six hardware). A

hardware interrupt is raised when Int[5:0]* signal goes active. A software interrupt is raised by setting the

IP[1]/IP[0] bit in Cause register. The significance of these interrupts is dependent upon the specific

system implementation.

Each of the eight interrupts can be masked individually by clearing its corresponding bit in the

IM(Interrupt Mask) field of Status register, and all interrupts can be masked at once by clearing IE bit of

Status register to 0.

8.19.2

Processing

The common exception vector is used as following:

•

In 32-bit mode, 0x8000 0180 (BEV

= 0)

0xbfc0 0380 (BEV

= 1)

•

In 64-bit mode, 0xffff ffff 8000 0180 (BEV

= 0)

0xffff ffff bfc0 0380 (BEV

= 1

When the processor is in the doze or halt operation mode, it is returned to the normal operation mode by

an interrupt.

8.19.3

Servicing

If the interrupt is caused by one of the two software-generated exceptions (SW1 or SW0), the interrupt

condition is cleared by setting the corresponding Cause register bit to 0.

If the interrupt is hardware-generated, the interrupt condition is cleared by correcting the condition

causing the interrupt pin to be asserted.

If the timer interrupt is caused, the interrupt condition is cleared by changing the value of the Compare

Interrupts are not acceptable when the settings of the Status register are EXL = 1 and ERL = 1.

Note:

Due to the write buffer, a store to an external device will not necessary occur until after

other instructions in the pipeline finish. Thus, the user must ensure that the store will

occur before the return from exception instruction (ERET) is executed otherwise the

interrupt may be serviced again even though there should be no interrupt pending.

TMPR4956C Datasheet(PDF) 147 Page - Toshiba Semiconductor