TMPR4956C datasheet(144/286 Pages) TOSHIBA

144 / 286 page

Chapter 8 CPU Exception

8-16

8.16 Reserved Instruction Exception

8.16.1

Cause

The Reserved Instruction exception occurs when one of the following condition occurs:

•

an attempt is made to execute an instruction with an undefined major opcode (bits 31-26)

•

an attempt is made to execute a SPECIAL instruction with an undefined minor opcode (bits 5-0)

•

an attempt is made to execute a REGIMM instruction with an undefined minor opcode (bits

20-16)

•

an attempt is made to execute 64-bit operations in 32-bit mode when in User or Supervisor

modes

•

an attempt is made to execute a COPz rs instruction with an undefined minor opcode (bits

25-21)

•

an attempt is made to execute a COPz rt instruction with an undefined minor opcode (bits

20-16)

64-bit operations are always valid in Kernel mode regardless of the value of the KX bit in Status

8.16.2

Processing

The common exception vector is used for this exception, and the RI code in Cause register is set.

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and the BD bit of Cause register is set to 1.

8.16.3

Servicing

No instruction in the MIPS ISA are currently interpreted. The process executing at the time of this

exception is handed an illegal instruction/reserved operand fault signal. This error is usually fatal.

TMPR4956C Datasheet(PDF) 144 Page - Toshiba Semiconductor