TMPR4956C datasheet(140/286 Pages) TOSHIBA

Part #	TMPR4956C

Description	64-Bit TX System RISC TX49 Family

PDF	286 Pages

Scroll/Zoom	100%

Manufacturer	TOSHIBA [Toshiba Semiconductor]

Direct Link	http://www.semicon.toshiba.co.jp/eng

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140 / 286 page

Chapter 8 CPU Exception

8-12

8.12 Integer Overflow Exception

8.12.1

Cause

The Integer Overflow exception occurs when ADD, ADDI, SUB, DADD, DADDI or DSUB

instruction results in a 2’s complement overflow. This exception is not maskable.

8.12.2

Processing

The common exception vector is used for this exception, and the Ov code in Cause register is set.

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and BD bit of Cause register is set to 1.

8.12.3

Servicing

The process executing at the time of the exception is handed a floating-point exception signal or integer

overflow signal. This error is usually fatal to the current process.

TMPR4956C Datasheet(PDF) 140 Page - Toshiba Semiconductor