TMPR4956C datasheet(136/286 Pages) TOSHIBA

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Chapter 8 CPU Exception

8-8

8.9

TLB Invalid Exception

8.9.1

Cause

The TLB Invalid exception occurs when a virtual address reference matches a TLB entry that is marked

invalid (TLB valid bit cleared). This exception is not maskable.

8.9.2

Processing

The common exception vector is used for this exception. When this exception occurs, TLBL or TLBS

code is set in the ExcCode field of Cause register. This code indicates whether the instruction, as shown

by EPC register and BD bit of Cause register, caused the miss by an instruction reference, load operation,

or store operation.

When this exception occurs:

•

BadVAddr, Context, XContext and EntryHi registers hold the virtual address failed address

translation

•

EntryHi register contains ASID from which the translation fault occurred, too

•

A valid address in which to place the replacement TLB entry is contained into Random register

•

The contents of EntryLo register are undefined

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and BD bit of Cause register is set to 1.

8.9.3

Servicing

A TLB entry is typically marked invalid when one of the following is true:

•

a virtual address does not exist

•

the virtual address exists, but is not in main memory (a page fault)

•

a trap is desired on any reference to the page (for example, to maintain a reference bit or during

debug)

After servicing the cause of a TLB Invalid exception, the TLB entry is located with TLB Probe (TLBP)

instruction, and replaced by an entry with that entry’s Valid bit set.

TMPR4956C Datasheet(PDF) 136 Page - Toshiba Semiconductor