TMPR4956C datasheet(137/286 Pages) TOSHIBA

137 / 286 page

Chapter 8 CPU Exception

8-9

8.10 TLB Modified Exception

8.10.1

Cause

The TLB Modified exception occurs when a store operation virtual address reference to memory

matches a TLB entry that is marked valid but is not dirty and therefore is not writable. This exception is

not maskable.

8.10.2

Processing

The common exception vector is used for this exception, and Mod code in Cause register is set.

When this exception occurs:

•

BadVAddr, Context, XContext and EntryHi registers hold the virtual address failed address

translation

•

EntryHi register contains ASID from which the translation fault occurred, too

•

The contents of EntryLo register are undefined

If EXL bit of Status register is only set to 0, the following operation is executed. EPC register points to

the address of the instruction causing the exception. If, however, the affected instruction was in the branch

delay slot (for execution during a branch), the immediately preceding branch instruction address is

retained in EPC register and BD bit of Cause register is set to 1.

8.10.3

Servicing

The kernel uses the failed virtual address or virtual page number to identify the corresponding access

control information. The page identified may or may not permit write accesses; if writes are not permitted,

a write protection violation occurs.

If write accessed are permitted, the page frame is marked dirty/writable by the kernel in its own data

structures. The TLB Probe (TLBP) instruction places the index of the TLB entry that must be altered into

the Index register. The EntryLo register is loaded with a word containing the physical page frame and

access control bits (with the D bit set), and the EntryHi and EntryLo registers are written into the TLB.

TMPR4956C Datasheet(PDF) 137 Page - Toshiba Semiconductor