TMPR4956C datasheet(133/286 Pages) TOSHIBA

133 / 286 page

Chapter 8 CPU Exception

8-5

8.6

NMI (Non-maskable Interrupt) Exception

8.6.1

Cause

The NMI (Non-maskable Interrupt) exception occurs at the falling edge of the NMI* signal. This

interrupt is not maskable, and occurs regardless of the EXL, ERL and IE bits of the Status register.

8.6.2

Processing

The same special interrupt vector as for ColdReset/SoftReset exception (virtual address: 0xbfc0_0000/

0xffff_ffff_bfc0_0000). This vector is located within unmapped and uncached area so that the cache and

TLB need not be initialized to process this exception. When this exception occurs, the SR bit of Status

Because NMI exception can occur in the midst of another exception, it is not normally possible to

continue program execution after servicing NMI exception.

Unlike the ColdReset/SoftReset exception, but like other exceptions, this exception occurs at an

instruction boundary. The state of the primary cache and memory system are preserved by this exception.

All register contents are retained except for the following.

•

ErrorEPC register, which contains the restart PC

If the exception-causing instruction is in a branch delay slot, the ErrorEPC register points at the

preceding branch instruction.

•

ERL, SR and BEV bits of the Status register, which is set to 1.

8.6.3

Servicing

The NMI exception is serviced by saving the current processor state for diagnostic purposes, and

reinitializing the system for the ColdReset exception.

TMPR4956C Datasheet(PDF) 133 Page - Toshiba Semiconductor