TMPR4956C datasheet(131/286 Pages) TOSHIBA

131 / 286 page

Chapter 8 CPU Exception

8-3

8.4

ColdReset Exception

8.4.1

Cause

This ColdReset exception occurs when the ColdReset* signal is asserted and then deasserted. This

exception is not maskable.

8.4.2

Processing

A special interrupt vector that resides in an unmapped and uncached area is used. It is therefore not

necessary for hardware to initialize TLB and cache memory in order to process this exception. The vector

location of this exception is:

•

In 32-bit mode, 0xbfc0 0000 (virtual address), 0x1fc0_0000 (physical address)

•

In 64-bit mode, 0xffff ffff bfc0 0000 (virtual address), 0x1fc0_0000 (physical address)

The most register’s contents are cleared when this exception occurs. The values of these bits are listed

into the table of Chapter 3.

Valid bits, Lock bits and FIFO replacement bits in the instruction cache are all cleared to 0. W bits, CS

bits, Lock bits and FIFO replacement bits in the data cache are all cleared to 0.

If a ColdReset exception occurs during bus cycle, the current bus cycle is aborted and an exception is

taken.

8.4.3

Servicing

The ColdReset exception is serviced by;

•

initializing all registers, coprocessor registers, caches and the memory system

•

performing diagnostic tests

•

bootstrapping the operating system

TMPR4956C Datasheet(PDF) 131 Page - Toshiba Semiconductor